A low power reconfigurable DCT architecture to trade off image quality for computational complexity

Jongsun Park, Kaushik Roy

Research output: Chapter in Book/Report/Conference proceedingConference contribution

21 Citations (Scopus)

Abstract

We present a low power reconfigurable DCT design, which achieves considerable computational complexity reduction in DCT operation with minimum image quality degradation. The approach is based on the modification of DCT bases in a bit-wise manner. Different computational complexity/image quality trade off levels are presented and a reconfigurable architecture, which can dynamically change from one trade off level to another, is also proposed. The reconfigurable DCT architecture can achieve power savings ranging from 20% to 70% for 5 different trade off levels.

Original languageEnglish
Title of host publicationICASSP, IEEE International Conference on Acoustics, Speech and Signal Processing - Proceedings
Volume5
Publication statusPublished - 2004
Externally publishedYes
EventProceedings - IEEE International Conference on Acoustics, Speech, and Signal Processing - Montreal, Que, Canada
Duration: 2004 May 172004 May 21

Other

OtherProceedings - IEEE International Conference on Acoustics, Speech, and Signal Processing
CountryCanada
CityMontreal, Que
Period04/5/1704/5/21

ASJC Scopus subject areas

  • Electrical and Electronic Engineering
  • Signal Processing
  • Acoustics and Ultrasonics

Fingerprint Dive into the research topics of 'A low power reconfigurable DCT architecture to trade off image quality for computational complexity'. Together they form a unique fingerprint.

  • Cite this

    Park, J., & Roy, K. (2004). A low power reconfigurable DCT architecture to trade off image quality for computational complexity. In ICASSP, IEEE International Conference on Acoustics, Speech and Signal Processing - Proceedings (Vol. 5)