A low-power reduced swing single clock flip-flop

Chulwoo Kim, Sung Mo Steve Kang

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

A reduced swing single clock flip-flop (RS/sup 2/CFF) is developed to reduce power consumption significantly compared to conventional FFs. RS/sup 2/CFF avoids unnecessary internal node transition and reduce fighting currents. The overall power saving in flip-flop operation is estimated to be 33% with additional 64% power savings in clock network.

Original languageEnglish
Title of host publicationISCAS 2001 - 2001 IEEE International Symposium on Circuits and Systems, Conference Proceedings
Pages806-809
Number of pages4
DOIs
Publication statusPublished - 2001
Externally publishedYes
Event2001 IEEE International Symposium on Circuits and Systems, ISCAS 2001 - Sydney, NSW, Australia
Duration: 2001 May 62001 May 9

Publication series

NameISCAS 2001 - 2001 IEEE International Symposium on Circuits and Systems, Conference Proceedings
Volume4

Other

Other2001 IEEE International Symposium on Circuits and Systems, ISCAS 2001
CountryAustralia
CitySydney, NSW
Period01/5/601/5/9

ASJC Scopus subject areas

  • Hardware and Architecture
  • Electrical and Electronic Engineering

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  • Cite this

    Kim, C., & Kang, S. M. S. (2001). A low-power reduced swing single clock flip-flop. In ISCAS 2001 - 2001 IEEE International Symposium on Circuits and Systems, Conference Proceedings (pp. 806-809). [922360] (ISCAS 2001 - 2001 IEEE International Symposium on Circuits and Systems, Conference Proceedings; Vol. 4). https://doi.org/10.1109/ISCAS.2001.922360