A low-power reduced swing single clock flip-flop

Chulwoo Kim, Sung Mo Steve Kang

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

A reduced swing single clock flip-flop (RS/sup 2/CFF) is developed to reduce power consumption significantly compared to conventional FFs. RS/sup 2/CFF avoids unnecessary internal node transition and reduce fighting currents. The overall power saving in flip-flop operation is estimated to be 33% with additional 64% power savings in clock network.

Original languageEnglish
Title of host publicationISCAS 2001 - 2001 IEEE International Symposium on Circuits and Systems, Conference Proceedings
Pages806-809
Number of pages4
Volume4
DOIs
Publication statusPublished - 2001 Dec 1
Externally publishedYes
Event2001 IEEE International Symposium on Circuits and Systems, ISCAS 2001 - Sydney, NSW, Australia
Duration: 2001 May 62001 May 9

Other

Other2001 IEEE International Symposium on Circuits and Systems, ISCAS 2001
CountryAustralia
CitySydney, NSW
Period01/5/601/5/9

Fingerprint

Flip flop circuits
Clocks
Electric power utilization

ASJC Scopus subject areas

  • Hardware and Architecture
  • Electrical and Electronic Engineering

Cite this

Kim, C., & Kang, S. M. S. (2001). A low-power reduced swing single clock flip-flop. In ISCAS 2001 - 2001 IEEE International Symposium on Circuits and Systems, Conference Proceedings (Vol. 4, pp. 806-809). [922360] https://doi.org/10.1109/ISCAS.2001.922360

A low-power reduced swing single clock flip-flop. / Kim, Chulwoo; Kang, Sung Mo Steve.

ISCAS 2001 - 2001 IEEE International Symposium on Circuits and Systems, Conference Proceedings. Vol. 4 2001. p. 806-809 922360.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Kim, C & Kang, SMS 2001, A low-power reduced swing single clock flip-flop. in ISCAS 2001 - 2001 IEEE International Symposium on Circuits and Systems, Conference Proceedings. vol. 4, 922360, pp. 806-809, 2001 IEEE International Symposium on Circuits and Systems, ISCAS 2001, Sydney, NSW, Australia, 01/5/6. https://doi.org/10.1109/ISCAS.2001.922360
Kim C, Kang SMS. A low-power reduced swing single clock flip-flop. In ISCAS 2001 - 2001 IEEE International Symposium on Circuits and Systems, Conference Proceedings. Vol. 4. 2001. p. 806-809. 922360 https://doi.org/10.1109/ISCAS.2001.922360
Kim, Chulwoo ; Kang, Sung Mo Steve. / A low-power reduced swing single clock flip-flop. ISCAS 2001 - 2001 IEEE International Symposium on Circuits and Systems, Conference Proceedings. Vol. 4 2001. pp. 806-809
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