A low-power small-area ± 7.28-ps-Jitter 1-GHz DLL-based clock generator

Chulwoo Kim, In Chul Hwang, Sung Mo Steve Kang

Research output: Contribution to journalArticlepeer-review

86 Citations (Scopus)


In this paper, a delay-locked loop (DLL)-based clock generator is presented. Although a DLL-based clock generator requires a clean reference signal, it has several inherent advantages over conventional phase-locked-loop-based clock generators, i.e., no jitter accumulation, fast locking, stable loop operation, and easy integration of the loop filter. We propose a phase detector with a reset circuitry and a new frequency multiplier to overcome the limited locking range and frequency multiplication problems of the conventional DLL-based system. Fabricated in a 0.35-μm CMOS process, our DLL-based clock generator occupies 0.07 mm2 of area and consumes 42.9 mW of power. It operates in the frequency range of 120 MHz-1.1 GHz and has a measured cycle-to-cycle jitter of ±7.28 ps at 1 GHz. The die area, peak-to-peak, and rms jitter are the smallest compared to those of reported high-frequency clock multipliers.

Original languageEnglish
Pages (from-to)1414-1420
Number of pages7
JournalIEEE Journal of Solid-State Circuits
Issue number11
Publication statusPublished - 2002 Nov
Externally publishedYes


  • Clock generator
  • Delay-locked loops (DLLs)
  • Frequency multiplication
  • Limited locking range
  • Low jitter
  • Phase detector (PD)

ASJC Scopus subject areas

  • Electrical and Electronic Engineering


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