A low-power tournament branch predictor

Sung Woo Chung, Gi Ho Park, Sung Bae Park

Research output: Contribution to journalArticle

Abstract

This letter proposes a low-power tournament branch predictor, in which the number of accesses to the branch predictors (local predictor or global predictor) is reduced. Analysis results with Samsung Memory Compiler show that the proposed branch predictor reduces the power consumption by 24-45%, compared to the conventional tournament branch predictor, not requiring any additional storage arrays, not incurring any additional delay and never harming accuracy.

Original languageEnglish
Pages (from-to)1962-1964
Number of pages3
JournalIEICE Transactions on Information and Systems
VolumeE87-D
Issue number7
Publication statusPublished - 2004 Jul
Externally publishedYes

Keywords

  • Global history
  • Local history
  • Low-power design
  • Memory compiler
  • Microarchitecture
  • Tournament branch predictor

ASJC Scopus subject areas

  • Software
  • Hardware and Architecture
  • Computer Vision and Pattern Recognition
  • Electrical and Electronic Engineering
  • Artificial Intelligence

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