Abstract
This letter proposes a low-power tournament branch predictor, in which the number of accesses to the branch predictors (local predictor or global predictor) is reduced. Analysis results with Samsung Memory Compiler show that the proposed branch predictor reduces the power consumption by 24-45%, compared to the conventional tournament branch predictor, not requiring any additional storage arrays, not incurring any additional delay and never harming accuracy.
| Original language | English |
|---|---|
| Pages (from-to) | 1962-1964 |
| Number of pages | 3 |
| Journal | IEICE Transactions on Information and Systems |
| Volume | E87-D |
| Issue number | 7 |
| Publication status | Published - 2004 Jul |
| Externally published | Yes |
Keywords
- Global history
- Local history
- Low-power design
- Memory compiler
- Microarchitecture
- Tournament branch predictor
ASJC Scopus subject areas
- Software
- Hardware and Architecture
- Computer Vision and Pattern Recognition
- Electrical and Electronic Engineering
- Artificial Intelligence