A low-swing clock double-edge triggered flip-flop

Chulwoo Kim, Sung Mo Kang

Research output: Contribution to journalArticle

58 Citations (Scopus)

Abstract

A low-swing clock double-edge triggered flip-flop (LSDFF) is developed to reduce power consumption significantly compared to conventional flip-flops. The LSDFF avoids unnecessary internal node transitions to reduce power consumption. In addition, power consumption in the clock tree is reduced because LSDFF uses a double-edge triggered operation as well as a low-swing clock. To prevent performance degradation of the LSDFF due to low-swing clock, low-V t transistors are used for the clocked transistors without significant leakage current problems. The power saving in flip-flop operation is estimated to be 28.6% to 49.6% with additional 78% power saving in the clock network.

Original languageEnglish
Pages (from-to)648-652
Number of pages5
JournalIEEE Journal of Solid-State Circuits
Volume37
Issue number5
DOIs
Publication statusPublished - 2002 May 1
Externally publishedYes

Fingerprint

Flip flop circuits
Clocks
Electric power utilization
Transistors
Leakage currents
Degradation

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

Cite this

A low-swing clock double-edge triggered flip-flop. / Kim, Chulwoo; Kang, Sung Mo.

In: IEEE Journal of Solid-State Circuits, Vol. 37, No. 5, 01.05.2002, p. 648-652.

Research output: Contribution to journalArticle

@article{731dda43bc8540b4ba45c8e40679dbf6,
title = "A low-swing clock double-edge triggered flip-flop",
abstract = "A low-swing clock double-edge triggered flip-flop (LSDFF) is developed to reduce power consumption significantly compared to conventional flip-flops. The LSDFF avoids unnecessary internal node transitions to reduce power consumption. In addition, power consumption in the clock tree is reduced because LSDFF uses a double-edge triggered operation as well as a low-swing clock. To prevent performance degradation of the LSDFF due to low-swing clock, low-V t transistors are used for the clocked transistors without significant leakage current problems. The power saving in flip-flop operation is estimated to be 28.6{\%} to 49.6{\%} with additional 78{\%} power saving in the clock network.",
author = "Chulwoo Kim and Kang, {Sung Mo}",
year = "2002",
month = "5",
day = "1",
doi = "10.1109/4.997859",
language = "English",
volume = "37",
pages = "648--652",
journal = "IEEE Journal of Solid-State Circuits",
issn = "0018-9200",
publisher = "Institute of Electrical and Electronics Engineers Inc.",
number = "5",

}

TY - JOUR

T1 - A low-swing clock double-edge triggered flip-flop

AU - Kim, Chulwoo

AU - Kang, Sung Mo

PY - 2002/5/1

Y1 - 2002/5/1

N2 - A low-swing clock double-edge triggered flip-flop (LSDFF) is developed to reduce power consumption significantly compared to conventional flip-flops. The LSDFF avoids unnecessary internal node transitions to reduce power consumption. In addition, power consumption in the clock tree is reduced because LSDFF uses a double-edge triggered operation as well as a low-swing clock. To prevent performance degradation of the LSDFF due to low-swing clock, low-V t transistors are used for the clocked transistors without significant leakage current problems. The power saving in flip-flop operation is estimated to be 28.6% to 49.6% with additional 78% power saving in the clock network.

AB - A low-swing clock double-edge triggered flip-flop (LSDFF) is developed to reduce power consumption significantly compared to conventional flip-flops. The LSDFF avoids unnecessary internal node transitions to reduce power consumption. In addition, power consumption in the clock tree is reduced because LSDFF uses a double-edge triggered operation as well as a low-swing clock. To prevent performance degradation of the LSDFF due to low-swing clock, low-V t transistors are used for the clocked transistors without significant leakage current problems. The power saving in flip-flop operation is estimated to be 28.6% to 49.6% with additional 78% power saving in the clock network.

UR - http://www.scopus.com/inward/record.url?scp=0036564730&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=0036564730&partnerID=8YFLogxK

U2 - 10.1109/4.997859

DO - 10.1109/4.997859

M3 - Article

AN - SCOPUS:0036564730

VL - 37

SP - 648

EP - 652

JO - IEEE Journal of Solid-State Circuits

JF - IEEE Journal of Solid-State Circuits

SN - 0018-9200

IS - 5

ER -