A low-swing clock double-edge triggered flip-flop

C. Kim, S. M. Kang

Research output: Contribution to conferencePaperpeer-review

17 Citations (Scopus)

Abstract

A low-swing clock double-edge triggered flip-flop (LSDFF) is developed to reduce power consumption significantly compared to conventional FFs. LSDFF avoids unnecessary internal node transition and reduce fighting currents. The overall power saving in flip-flop operation is estimated to be 30.2 to 50.8% with additional 78% power savings in clock network.

Original languageEnglish
Pages183-186
Number of pages4
Publication statusPublished - 2001
Externally publishedYes
Event2001 VLSI Circuits Symposium - Kyoto, Japan
Duration: 2001 Jun 142001 Jun 16

Other

Other2001 VLSI Circuits Symposium
Country/TerritoryJapan
CityKyoto
Period01/6/1401/6/16

ASJC Scopus subject areas

  • Electronic, Optical and Magnetic Materials
  • Electrical and Electronic Engineering

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