A multi-gigabit CMOS serial link transceiver using jitter tolerant delay locked loop

Byeong Chun So, Won Suk Hwang, Soo-Won Kim

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

A multi-gigabit CMOS serial link transceiver is described. To reduce the jitter of the clock, it uses a multiphase Delay Locked Loop(DLL) when it receives the serialized data. The circuit operates with a parallel sampling technique to reduce the speed requirements of the circuits. The analog phase detector provides a linear characteristic while deserializing the data with no phase offset. The proposed circuit is designed using 0.25um CMOS technology. It is capable of recovering data at a speed of 2.5Gbps.

Original languageEnglish
Title of host publication2003 IEEE Conference on Electron Devices and Solid-State Circuits, EDSSC 2003
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages171-174
Number of pages4
ISBN (Print)0780377494, 9780780377493
DOIs
Publication statusPublished - 2003
EventIEEE Conference on Electron Devices and Solid-State Circuits, EDSSC 2003 - Tsimshatsui, Kowloon, Hong Kong
Duration: 2003 Dec 162003 Dec 18

Other

OtherIEEE Conference on Electron Devices and Solid-State Circuits, EDSSC 2003
CountryHong Kong
CityTsimshatsui, Kowloon
Period03/12/1603/12/18

Keywords

  • Clock and Data Recovery(CDR)
  • Delay Locked Loop(DLL)
  • Low jitter
  • Multiphase
  • Phase detector
  • PLL

ASJC Scopus subject areas

  • Hardware and Architecture
  • Electrical and Electronic Engineering

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  • Cite this

    So, B. C., Hwang, W. S., & Kim, S-W. (2003). A multi-gigabit CMOS serial link transceiver using jitter tolerant delay locked loop. In 2003 IEEE Conference on Electron Devices and Solid-State Circuits, EDSSC 2003 (pp. 171-174). [1283508] Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/EDSSC.2003.1283508