A near-threshold all-digital PLL with a bootstrapped DCO using low-dropout regulator for mitigating PVT-variations

Sangsu Lee, Jaehun Jun, Chulwoo Kim

Research output: Chapter in Book/Report/Conference proceedingConference contribution

2 Citations (Scopus)

Abstract

Low-power operation is essential for emerging fields in the circuit design such as Internet of Things(IoT) and Biomedical applications. Since the supply voltage is a major factor that affects the total power consumption, design in Near-Threshold Voltage(NTV) region which is known to have the advantages of both power-saving and well-performance can be an effective way to overcome the constraints. This paper presents an ADPLL(All-Digital Phase-Locked Loop) operating in NTV region. Bootstrapped ring oscillator(BTRO) is used for the PVT tolerance of the Digitally Controlled Oscillator(DCO) and Low-Dropout Regulator(LDO) is adopted for the optimal control of the supply voltage. This ADPLL operates at 480MHz with a power consumption of 152uW under a supply voltage of 0.55V.

Original languageEnglish
Title of host publicationProceedings - International SoC Design Conference 2017, ISOCC 2017
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages180-181
Number of pages2
ISBN (Electronic)9781538622858
DOIs
Publication statusPublished - 2018 May 29
Event14th International SoC Design Conference, ISOCC 2017 - Seoul, Korea, Republic of
Duration: 2017 Nov 52017 Nov 8

Other

Other14th International SoC Design Conference, ISOCC 2017
CountryKorea, Republic of
CitySeoul
Period17/11/517/11/8

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Keywords

  • All-Digital Phase-Locked Loop(ADPLL)
  • Bootstrapped Ring Oscillator(BTRO)
  • Low-Dropout Regulator(LDO)
  • Near-Threshold Voltage(NTV)
  • Power Supply Rejection(PSR)

ASJC Scopus subject areas

  • Hardware and Architecture
  • Electrical and Electronic Engineering
  • Electronic, Optical and Magnetic Materials

Cite this

Lee, S., Jun, J., & Kim, C. (2018). A near-threshold all-digital PLL with a bootstrapped DCO using low-dropout regulator for mitigating PVT-variations. In Proceedings - International SoC Design Conference 2017, ISOCC 2017 (pp. 180-181). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ISOCC.2017.8368869