A Near-Threshold Voltage Oriented Digital Cell Library for High-Energy Efficiency and Optimized Performance in 65nm CMOS Process

Jaehun Jun, Jaegeun Song, Chulwoo Kim

Research output: Contribution to journalArticle

6 Citations (Scopus)

Abstract

A digital cell library operating in the near-threshold voltage (NTV) region is presented to obtain both high energy efficiency and optimized performance. The proposed library oriented to the NTV region is optimized using the parasitic effects of nanometer process technology and a body-biasing technique. To maximize the energy efficiency, the proposed cell library utilized the minimum width allowed by the process as the base width unit. To enhance the performance, digital cells were developed with various strengths whose sizing method relies on the minimum unit width, reverse short channel effect, and inverse narrow width effect. An asymmetric gate-length scheme is applied to multi-fan-in logic gates to increase the performance. Also, the proposed TAP cell was added, combined with an inverter-based forward body-biasing circuit. Finally, a library with 59 cells was developed and made available for synthesis and automatic layout and the proposed NTV library was then evaluated with ISCAS benchmark logics. The proposed NTV cell library shows more than 10~ 20% less energy consumption compared with a conventional digital cell library using minimum gate length and monolithic width. EDP is also increased by 10~ 20% with a simply controlled body-biasing scheme compared with the conventional one.

Original languageEnglish
JournalIEEE Transactions on Circuits and Systems I: Regular Papers
DOIs
Publication statusAccepted/In press - 2017 Oct 27

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Threshold voltage
Energy efficiency
Logic gates
Energy utilization
Networks (circuits)

Keywords

  • CMOS integrated circuit
  • Computer architecture
  • Delays
  • digital cell library
  • EDP
  • energy efficiency
  • forward body biasing
  • INWE.
  • Libraries
  • Logic gates
  • Microprocessors
  • near threshold voltage
  • Optimization
  • Power demand
  • RSCE

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

Cite this

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title = "A Near-Threshold Voltage Oriented Digital Cell Library for High-Energy Efficiency and Optimized Performance in 65nm CMOS Process",
abstract = "A digital cell library operating in the near-threshold voltage (NTV) region is presented to obtain both high energy efficiency and optimized performance. The proposed library oriented to the NTV region is optimized using the parasitic effects of nanometer process technology and a body-biasing technique. To maximize the energy efficiency, the proposed cell library utilized the minimum width allowed by the process as the base width unit. To enhance the performance, digital cells were developed with various strengths whose sizing method relies on the minimum unit width, reverse short channel effect, and inverse narrow width effect. An asymmetric gate-length scheme is applied to multi-fan-in logic gates to increase the performance. Also, the proposed TAP cell was added, combined with an inverter-based forward body-biasing circuit. Finally, a library with 59 cells was developed and made available for synthesis and automatic layout and the proposed NTV library was then evaluated with ISCAS benchmark logics. The proposed NTV cell library shows more than 10~ 20{\%} less energy consumption compared with a conventional digital cell library using minimum gate length and monolithic width. EDP is also increased by 10~ 20{\%} with a simply controlled body-biasing scheme compared with the conventional one.",
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AB - A digital cell library operating in the near-threshold voltage (NTV) region is presented to obtain both high energy efficiency and optimized performance. The proposed library oriented to the NTV region is optimized using the parasitic effects of nanometer process technology and a body-biasing technique. To maximize the energy efficiency, the proposed cell library utilized the minimum width allowed by the process as the base width unit. To enhance the performance, digital cells were developed with various strengths whose sizing method relies on the minimum unit width, reverse short channel effect, and inverse narrow width effect. An asymmetric gate-length scheme is applied to multi-fan-in logic gates to increase the performance. Also, the proposed TAP cell was added, combined with an inverter-based forward body-biasing circuit. Finally, a library with 59 cells was developed and made available for synthesis and automatic layout and the proposed NTV library was then evaluated with ISCAS benchmark logics. The proposed NTV cell library shows more than 10~ 20% less energy consumption compared with a conventional digital cell library using minimum gate length and monolithic width. EDP is also increased by 10~ 20% with a simply controlled body-biasing scheme compared with the conventional one.

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