TY - JOUR
T1 - A new class of charge-trap flash memory with resistive switching mechanisms
AU - An, Ho Myoung
AU - Lee, Eui Bok
AU - Kim, Hee Dong
AU - Seo, Yu Jeong
AU - Kim, Tae Geun
N1 - Funding Information:
Manuscript received April 15, 2010; revised June 25, 2010; accepted July 20, 2010. Date of publication August 19, 2010; date of current version September 22, 2010. This work was supported in part by the National Research Foundation (NRF) of Korea under Grant K20901000002-09E0100-00210, by the Basic Science Research Program under an NRF grant funded by the Ministry of Education, Science, and Technology (Quantum Photonic Science Research Center), and by the Seoul R&BD Program. The review of this paper was arranged by Editor J. C. S. Woo.
PY - 2010/10
Y1 - 2010/10
N2 - This paper presents a new class of charge-trap Flash memory device with resistive switching mechanisms. We propose a fused memory scheme using a structure of metal/Pr0.7 Ca0.3MnO3 (PCMO)/nitride/oxide/silicon to graft fast-switching features of resistive random access memory onto high-density silicon/oxide/nitride/oxide/silicon memory structures. In this scheme, both program and erase (P/E) are performed by the conduction of the carriers that are injected from the gate into the nitride layer through the PCMO, which is a resistive switching material; the resistance state determines whether a program or erase function is performed. In the proposed memory devices, we observed improved memory characteristics, including the currentvoltage hysteresis having a resistive ratio exceeding three orders of magnitude at a set voltage of ± 4.5 V, a memory window of 2.3 V, a P/E speed of 100 ns/1 ms, data retention of ten years, and endurance of 10 5 P/E cycles. This approach will offer critical clues about how one can best implement universal features of nonvolatile memories in a single chip.
AB - This paper presents a new class of charge-trap Flash memory device with resistive switching mechanisms. We propose a fused memory scheme using a structure of metal/Pr0.7 Ca0.3MnO3 (PCMO)/nitride/oxide/silicon to graft fast-switching features of resistive random access memory onto high-density silicon/oxide/nitride/oxide/silicon memory structures. In this scheme, both program and erase (P/E) are performed by the conduction of the carriers that are injected from the gate into the nitride layer through the PCMO, which is a resistive switching material; the resistance state determines whether a program or erase function is performed. In the proposed memory devices, we observed improved memory characteristics, including the currentvoltage hysteresis having a resistive ratio exceeding three orders of magnitude at a set voltage of ± 4.5 V, a memory window of 2.3 V, a P/E speed of 100 ns/1 ms, data retention of ten years, and endurance of 10 5 P/E cycles. This approach will offer critical clues about how one can best implement universal features of nonvolatile memories in a single chip.
KW - Charge-trap Flash (CTF)
KW - resistive random access memory (ReRAM)
KW - resistive switching
KW - silicon/oxide/nitride/oxide/silicon (SONOS)
KW - universal memory
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U2 - 10.1109/TED.2010.2063706
DO - 10.1109/TED.2010.2063706
M3 - Article
AN - SCOPUS:77957005281
VL - 57
SP - 2398
EP - 2404
JO - IEEE Transactions on Electron Devices
JF - IEEE Transactions on Electron Devices
SN - 0018-9383
IS - 10
M1 - 5551188
ER -