A new energy × delay-aware flip-flop

Inhwa Jung, Moo Young Kim, Dongsuk Shin, Seon Wook Kim, Chulwoo Kim

Research output: Contribution to journalArticle

Abstract

This paper describes the Differential Pass Transistor Pulsed Latch (DPTPL) which enhances D-Q delay and reduce power consumption using NMOS pass transistors and feedback PMOS transistors. The proposed flip-flop uses the characteristic of stronger drivability of NMOS transistor than that of transmission gate if the sum of total transistor width is the same. Positive feedback PMOS transistors enhance the speed of the latch as well as guarantee the full-swing of internal nodes. Also, the power consumption of proposed pulsed latch is reduced significantly due to the reduced clock load and smaller total transistor width compared to conventional differential flip-flops. DPTPL reduces E × D by 45.5 over ep-SFF. The simulations were performed in a 0.1 μm CMOS technology at 1.2 V supply voltage with 1.25 GHz clock frequency. copyright

Original languageEnglish
Pages (from-to)1552-1557
Number of pages6
JournalIEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
VolumeE89-A
Issue number6
DOIs
Publication statusPublished - 2006 Jun 1

Fingerprint

Flip flop circuits
Flip
Transistors
Power Consumption
Energy
Positive Feedback
Voltage
Internal
Clocks
Electric power utilization
Vertex of a graph
Gates (transistor)
Feedback
Simulation
Electric potential

Keywords

  • Flip-flop
  • High-speed
  • Low-power
  • Pulsed-latch

ASJC Scopus subject areas

  • Electrical and Electronic Engineering
  • Hardware and Architecture
  • Information Systems

Cite this

A new energy × delay-aware flip-flop. / Jung, Inhwa; Kim, Moo Young; Shin, Dongsuk; Kim, Seon Wook; Kim, Chulwoo.

In: IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, Vol. E89-A, No. 6, 01.06.2006, p. 1552-1557.

Research output: Contribution to journalArticle

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