A novel method for high-performance phase-locked loop

Youngshin Woo, Young Min Jang, Man Young Sung

Research output: Contribution to journalArticle

3 Citations (Scopus)

Abstract

In this paper, we propose a phase-locked loop (PLL) with dual PFDs and a modified loop filter in which advantages of both PFDs can be combined and the trade-off between acquisition behavior and locked behavior can be achieved. By operating the appropriate PFD connected to the well-adjusted charge pump and regulating the loop bandwidth to input frequency ratio with an input divider and a modified loop filter, an unlimited error detection range, a high frequency operation, a reduced dead zone and a higher speed lock-up time can be achieved. The proposed PLL structure is designed using 1.5 μm CMOS technology with 5 V supply voltage.

Original languageEnglish
Pages (from-to)53-63
Number of pages11
JournalJournal of Circuits, Systems and Computers
Volume13
Issue number1
DOIs
Publication statusPublished - 2004 Feb 1

Fingerprint

Phase locked loops
Error detection
Pumps
Bandwidth
Electric potential

Keywords

  • Dual PFDs
  • Fast-lock
  • High-frequency
  • Loop bandwidth
  • Loop filter
  • PLL

ASJC Scopus subject areas

  • Hardware and Architecture
  • Electrical and Electronic Engineering

Cite this

A novel method for high-performance phase-locked loop. / Woo, Youngshin; Jang, Young Min; Sung, Man Young.

In: Journal of Circuits, Systems and Computers, Vol. 13, No. 1, 01.02.2004, p. 53-63.

Research output: Contribution to journalArticle

Woo, Youngshin ; Jang, Young Min ; Sung, Man Young. / A novel method for high-performance phase-locked loop. In: Journal of Circuits, Systems and Computers. 2004 ; Vol. 13, No. 1. pp. 53-63.
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