A novel thin chip scale packaging of the RF-MEMS devices using ultra thin silicon

Yun Kwon Park, Yong Kook Kim, Hoon Kim, Duck Jung Lee, Chul Ju Kim, Byeong Kwon Ju, Jong Oh Park

Research output: Contribution to conferencePaper

7 Citations (Scopus)

Abstract

In this paper, as ultra thin silicon substrate was used as packaging substrate, we proposed ultra thin chip size RF-MEMS packaging technology that has vertical feed-through for low loss, as reduced the parasitic capacity. Thin silicon wafer with 50um thickness was fabricated to achieve short electric path, low loss and lightweight. And then via holes with the diameter of 60um were fabricated and was filled by the RIE and electroplating process. Also, the wafer level bumps were fabricated for simple, low cost, and fine patterning process. The measured S-parameter of packaged CPW(Co-planner waveguide) has the reflection loss of under -19 dB and the insertion loss of -0.54 -0.67 dB.

Original languageEnglish
Pages618-621
Number of pages4
Publication statusPublished - 2003
EventIEEE Sixteenth Annual International Conference on Micro Electro Mechanical Systems - Kyoto, Japan
Duration: 2003 Jan 192003 Jan 23

Other

OtherIEEE Sixteenth Annual International Conference on Micro Electro Mechanical Systems
CountryJapan
CityKyoto
Period03/1/1903/1/23

ASJC Scopus subject areas

  • Control and Systems Engineering
  • Mechanical Engineering
  • Electrical and Electronic Engineering

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  • Cite this

    Park, Y. K., Kim, Y. K., Kim, H., Lee, D. J., Kim, C. J., Ju, B. K., & Park, J. O. (2003). A novel thin chip scale packaging of the RF-MEMS devices using ultra thin silicon. 618-621. Paper presented at IEEE Sixteenth Annual International Conference on Micro Electro Mechanical Systems, Kyoto, Japan.