A one-cycle lock time slew-rate-controlled output driver

Young Ho Kwak, Inhwa Jung, Hyung Dong Lee, Young Jung Choi, Yogendera Kumar, Chulwoo Kim

Research output: Chapter in Book/Report/Conference proceedingConference contribution

23 Citations (Scopus)

Abstract

A low-power output-on-demand slew-rate-controlled output driver is presented. It has an open-loop digital scheme and a one-cycle lock time applicable to high-speed memory interfaces. The output driver maintains slew rate between 2.1 V/ns and 3.6V/ns for the SSTL interface. Fabricated in a 0.18μm CMOS process, the control block of the proposed driver occupies 0.009mm 2 and consumes 13.7mW at 1Gb/s. No external resistance is needed to calibrate the output resistance of the output driver.

Original languageEnglish
Title of host publicationDigest of Technical Papers - IEEE International Solid-State Circuits Conference
DOIs
Publication statusPublished - 2007 Sep 27
Event54th IEEE International Solid-State Circuits Conference, ISSCC 2007 - San Francisco, CA, United States
Duration: 2007 Feb 112007 Feb 15

Other

Other54th IEEE International Solid-State Circuits Conference, ISSCC 2007
CountryUnited States
CitySan Francisco, CA
Period07/2/1107/2/15

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ASJC Scopus subject areas

  • Electrical and Electronic Engineering
  • Hardware and Architecture

Cite this

Kwak, Y. H., Jung, I., Lee, H. D., Choi, Y. J., Kumar, Y., & Kim, C. (2007). A one-cycle lock time slew-rate-controlled output driver. In Digest of Technical Papers - IEEE International Solid-State Circuits Conference [4242438] https://doi.org/10.1109/ISSCC.2007.373467