A one-cycle lock time slew-rate-controlled output driver

Young Ho Kwak; Inhwa Jung; Hyung Dong Lee; Young Jung Choi; Yogendera Kumar; Chulwoo Kim

doi:10.1109/ISSCC.2007.373467

A one-cycle lock time slew-rate-controlled output driver

Young Ho Kwak, Inhwa Jung, Hyung Dong Lee, Young Jung Choi, Yogendera Kumar, Chulwoo Kim

School of Electrical Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

23 Citations (Scopus)

Abstract

A low-power output-on-demand slew-rate-controlled output driver is presented. It has an open-loop digital scheme and a one-cycle lock time applicable to high-speed memory interfaces. The output driver maintains slew rate between 2.1 V/ns and 3.6V/ns for the SSTL interface. Fabricated in a 0.18μm CMOS process, the control block of the proposed driver occupies 0.009mm² and consumes 13.7mW at 1Gb/s. No external resistance is needed to calibrate the output resistance of the output driver.

Original language	English
Title of host publication	2007 IEEE International Solid-State Circuits Conference, ISSCC - Digest of Technical Papers
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	408-410
Number of pages	3
ISBN (Print)	1424408539, 9781424408535
DOIs	https://doi.org/10.1109/ISSCC.2007.373467
Publication status	Published - 2007
Event	54th IEEE International Solid-State Circuits Conference, ISSCC 2007 - San Francisco, CA, United States Duration: 2007 Feb 11 → 2007 Feb 15

Publication series

Name	Digest of Technical Papers - IEEE International Solid-State Circuits Conference
ISSN (Print)	0193-6530

Other

Other	54th IEEE International Solid-State Circuits Conference, ISSCC 2007
Country/Territory	United States
City	San Francisco, CA
Period	07/2/11 → 07/2/15

ASJC Scopus subject areas

Electronic, Optical and Magnetic Materials
Electrical and Electronic Engineering

Access to Document

10.1109/ISSCC.2007.373467

Cite this

Kwak, Y. H., Jung, I., Lee, H. D., Choi, Y. J., Kumar, Y., & Kim, C. (2007). A one-cycle lock time slew-rate-controlled output driver. In 2007 IEEE International Solid-State Circuits Conference, ISSCC - Digest of Technical Papers (pp. 408-410). [4242438] (Digest of Technical Papers - IEEE International Solid-State Circuits Conference). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ISSCC.2007.373467

A one-cycle lock time slew-rate-controlled output driver. / Kwak, Young Ho; Jung, Inhwa; Lee, Hyung Dong et al.

2007 IEEE International Solid-State Circuits Conference, ISSCC - Digest of Technical Papers. Institute of Electrical and Electronics Engineers Inc., 2007. p. 408-410 4242438 (Digest of Technical Papers - IEEE International Solid-State Circuits Conference).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Kwak, YH, Jung, I, Lee, HD, Choi, YJ, Kumar, Y & Kim, C 2007, A one-cycle lock time slew-rate-controlled output driver. in 2007 IEEE International Solid-State Circuits Conference, ISSCC - Digest of Technical Papers., 4242438, Digest of Technical Papers - IEEE International Solid-State Circuits Conference, Institute of Electrical and Electronics Engineers Inc., pp. 408-410, 54th IEEE International Solid-State Circuits Conference, ISSCC 2007, San Francisco, CA, United States, 07/2/11. https://doi.org/10.1109/ISSCC.2007.373467

Kwak YH, Jung I, Lee HD, Choi YJ, Kumar Y, Kim C. A one-cycle lock time slew-rate-controlled output driver. In 2007 IEEE International Solid-State Circuits Conference, ISSCC - Digest of Technical Papers. Institute of Electrical and Electronics Engineers Inc. 2007. p. 408-410. 4242438. (Digest of Technical Papers - IEEE International Solid-State Circuits Conference). doi: 10.1109/ISSCC.2007.373467

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abstract = "A low-power output-on-demand slew-rate-controlled output driver is presented. It has an open-loop digital scheme and a one-cycle lock time applicable to high-speed memory interfaces. The output driver maintains slew rate between 2.1 V/ns and 3.6V/ns for the SSTL interface. Fabricated in a 0.18μm CMOS process, the control block of the proposed driver occupies 0.009mm2 and consumes 13.7mW at 1Gb/s. No external resistance is needed to calibrate the output resistance of the output driver.",

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AB - A low-power output-on-demand slew-rate-controlled output driver is presented. It has an open-loop digital scheme and a one-cycle lock time applicable to high-speed memory interfaces. The output driver maintains slew rate between 2.1 V/ns and 3.6V/ns for the SSTL interface. Fabricated in a 0.18μm CMOS process, the control block of the proposed driver occupies 0.009mm2 and consumes 13.7mW at 1Gb/s. No external resistance is needed to calibrate the output resistance of the output driver.

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A one-cycle lock time slew-rate-controlled output driver

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