A piecewise linear 10 bit DAC architecture with drain current modulation for compact LCD driver ICs

Yong Joon Jeon, Hyung Min Lee, Sung Woo Lee, Gyu Hyeong Cho, Hyoung Rae Kim, Yoon Kyung Choi, Myunghee Lee

Research output: Contribution to journalArticle

25 Citations (Scopus)

Abstract

A piecewise linear 10 bit DAC for LCD data driver with robust interpolation method of drain current modulation is presented. It has higher effective bit resolution than the linear 10 bit switched-capacitor DAC when applied to nonlinear liquid crystal characteristics. By adopting a simultaneous design flow based on the estimations for the mismatch and nonlinearity effects on channel driver performance, the proposed DAC accomplishes good DNL of 0.37 LSB and excellent channel uniformity such that the mean and the standard deviation of the maximum output voltage deviations are 6.35 mV and 0.54 mV, respectively. The data driver with the new interpolation shows 8.2% shrinkage of chip area in comparison with the conventional 8 bit data driver with R-DAC.

Original languageEnglish
Article number5342341
Pages (from-to)3659-3675
Number of pages17
JournalIEEE Journal of Solid-State Circuits
Volume44
Issue number12
DOIs
Publication statusPublished - 2009 Dec
Externally publishedYes

Keywords

  • Cascaded-dividing DAC
  • Data driver
  • Drain current modulation
  • Interpolation
  • LCD
  • Piecewise linear

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

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