Recently PDP market has been shrinking gradually, but the expansion of 3D (3 dimensional) TV provides a new opportunity to PDP of retrieving its market share by favor of its higher response speed over LCD. In this paper, we propose a novel processor-based decoupled PDP timing controller design which is flexible, and therefore meets the design requirements, i.e., to support rapid and low cost design revision. To generate high frequency signal in real-time without any undesired latency, we adopt a decoupled architecture to the PDP timing controller. The design also supports multi-clock domain signal generation by managing multiple threads. Taking advantage of the flexibility and programmability in software execution, the design for 2D (2 dimensional) can be also easily extended to 3D design with minor modification. We implemented a prototype system of the proposed design which successfully runs on FPGA attached to 42-inch and 50-inch PDP panels with high-definition (HD) resolution. The system generates multi-clock domain timing control signals at 100 MHz and 133 MHz simultaneously and the extension for 3D design has negligible resource increments over the 2D design.
- Decoupled Architecture
- Timing Controller
ASJC Scopus subject areas
- Media Technology
- Electrical and Electronic Engineering