A reconfigurable FIR filter architecture to trade off filter performance for dynamic power consumption

Seok Jae Lee, Ji Woong Choi, Seon Wook Kim, Jongsun Park

Research output: Contribution to journalArticle

34 Citations (Scopus)

Abstract

This paper presents an architectural approach to the design of low power reconfigurable finite impulse response (FIR) filter. The approach is well suited when the filter order is fixed and not changed for particular applications, and efficient trade-off between power savings and filter performance can be made using the proposed architecture. Generally, FIR filter has large amplitude variations in input data and coefficients. Considering the amplitude of both the filter coefficients and inputs, the proposed FIR filter dynamically changes the filter order. Mathematical analysis on power savings and filter performance degradation and its experimental results show that the proposed approach achieves significant power savings without seriously compromising the filter performance. The power savings is up to 41.9% with minor performance degradation, and the area overhead of the proposed scheme is less than 5.3% compared to the conventional approach.

Original languageEnglish
Article number5640702
Pages (from-to)2221-2228
Number of pages8
JournalIEEE Transactions on Very Large Scale Integration (VLSI) Systems
Volume19
Issue number12
DOIs
Publication statusPublished - 2011 Dec 1

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FIR filters
Electric power utilization
Degradation

Keywords

  • Approximate filtering
  • low power filter
  • reconfigurable design

ASJC Scopus subject areas

  • Electrical and Electronic Engineering
  • Hardware and Architecture
  • Software

Cite this

A reconfigurable FIR filter architecture to trade off filter performance for dynamic power consumption. / Lee, Seok Jae; Choi, Ji Woong; Kim, Seon Wook; Park, Jongsun.

In: IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 19, No. 12, 5640702, 01.12.2011, p. 2221-2228.

Research output: Contribution to journalArticle

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