A Refresh-Less eDRAM Macro with Embedded Voltage Reference and Selective Read for an Area and Power Efficient Viterbi Decoder

Woong Choi, Gyuseong Kang, Jongsun Park

Research output: Contribution to journalArticle

12 Citations (Scopus)

Abstract

This paper presents a Viterbi-specific 2T gain cell- based embedded DRAM (eDRAM) design for IEEE 802.11n WLAN application. In the proposed Viterbi decoder, refresh operations are completely removed in the eDRAM, by ensuring that the read-after-write period of survivor memory is shorter than the retention time of the gain cell. In order to facilitate the write operation with single-supply voltage, a beneficial read word-line (RWL) coupling technique is proposed. In this work, we also present a reference voltage generation scheme to support single-ended read operation. Thanks to the decoupled read and write structure of the gain cell, the proposed eDRAM can support dual-port operations without large area overhead, thus doubling the bandwidth of memories in the Viterbi decoder. To further reduce the area of the customized Viterbi memory, common redundant hardware between the memory peripheral and computational logics is identified and eliminated without latency overhead. The 4 bit soft-decision 64-state Viterbi decoder with 24 kb eDRAM (1-bank) is implemented in 65 nm CMOS process technology. The chip measurement results show 44% area and 39% power savings over the conventional SRAM-based Viterbi decoder implementation.

Original languageEnglish
Article number7174555
Pages (from-to)2451-2462
Number of pages12
JournalIEEE Journal of Solid-State Circuits
Volume50
Issue number10
DOIs
Publication statusPublished - 2015 Oct 1

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Dynamic random access storage
Macros
Data storage equipment
Electric potential
Computer peripheral equipment
Static random access storage
Wireless local area networks (WLAN)
Computer hardware
Bandwidth

Keywords

  • Application-specific memory
  • eDRAM
  • embedded memory
  • gain cell
  • reference voltage generator
  • Viterbi decoder

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

Cite this

A Refresh-Less eDRAM Macro with Embedded Voltage Reference and Selective Read for an Area and Power Efficient Viterbi Decoder. / Choi, Woong; Kang, Gyuseong; Park, Jongsun.

In: IEEE Journal of Solid-State Circuits, Vol. 50, No. 10, 7174555, 01.10.2015, p. 2451-2462.

Research output: Contribution to journalArticle

@article{a3432da457174d50a476b4e63ebc564d,
title = "A Refresh-Less eDRAM Macro with Embedded Voltage Reference and Selective Read for an Area and Power Efficient Viterbi Decoder",
abstract = "This paper presents a Viterbi-specific 2T gain cell- based embedded DRAM (eDRAM) design for IEEE 802.11n WLAN application. In the proposed Viterbi decoder, refresh operations are completely removed in the eDRAM, by ensuring that the read-after-write period of survivor memory is shorter than the retention time of the gain cell. In order to facilitate the write operation with single-supply voltage, a beneficial read word-line (RWL) coupling technique is proposed. In this work, we also present a reference voltage generation scheme to support single-ended read operation. Thanks to the decoupled read and write structure of the gain cell, the proposed eDRAM can support dual-port operations without large area overhead, thus doubling the bandwidth of memories in the Viterbi decoder. To further reduce the area of the customized Viterbi memory, common redundant hardware between the memory peripheral and computational logics is identified and eliminated without latency overhead. The 4 bit soft-decision 64-state Viterbi decoder with 24 kb eDRAM (1-bank) is implemented in 65 nm CMOS process technology. The chip measurement results show 44{\%} area and 39{\%} power savings over the conventional SRAM-based Viterbi decoder implementation.",
keywords = "Application-specific memory, eDRAM, embedded memory, gain cell, reference voltage generator, Viterbi decoder",
author = "Woong Choi and Gyuseong Kang and Jongsun Park",
year = "2015",
month = "10",
day = "1",
doi = "10.1109/JSSC.2015.2454241",
language = "English",
volume = "50",
pages = "2451--2462",
journal = "IEEE Journal of Solid-State Circuits",
issn = "0018-9200",
publisher = "Institute of Electrical and Electronics Engineers Inc.",
number = "10",

}

TY - JOUR

T1 - A Refresh-Less eDRAM Macro with Embedded Voltage Reference and Selective Read for an Area and Power Efficient Viterbi Decoder

AU - Choi, Woong

AU - Kang, Gyuseong

AU - Park, Jongsun

PY - 2015/10/1

Y1 - 2015/10/1

N2 - This paper presents a Viterbi-specific 2T gain cell- based embedded DRAM (eDRAM) design for IEEE 802.11n WLAN application. In the proposed Viterbi decoder, refresh operations are completely removed in the eDRAM, by ensuring that the read-after-write period of survivor memory is shorter than the retention time of the gain cell. In order to facilitate the write operation with single-supply voltage, a beneficial read word-line (RWL) coupling technique is proposed. In this work, we also present a reference voltage generation scheme to support single-ended read operation. Thanks to the decoupled read and write structure of the gain cell, the proposed eDRAM can support dual-port operations without large area overhead, thus doubling the bandwidth of memories in the Viterbi decoder. To further reduce the area of the customized Viterbi memory, common redundant hardware between the memory peripheral and computational logics is identified and eliminated without latency overhead. The 4 bit soft-decision 64-state Viterbi decoder with 24 kb eDRAM (1-bank) is implemented in 65 nm CMOS process technology. The chip measurement results show 44% area and 39% power savings over the conventional SRAM-based Viterbi decoder implementation.

AB - This paper presents a Viterbi-specific 2T gain cell- based embedded DRAM (eDRAM) design for IEEE 802.11n WLAN application. In the proposed Viterbi decoder, refresh operations are completely removed in the eDRAM, by ensuring that the read-after-write period of survivor memory is shorter than the retention time of the gain cell. In order to facilitate the write operation with single-supply voltage, a beneficial read word-line (RWL) coupling technique is proposed. In this work, we also present a reference voltage generation scheme to support single-ended read operation. Thanks to the decoupled read and write structure of the gain cell, the proposed eDRAM can support dual-port operations without large area overhead, thus doubling the bandwidth of memories in the Viterbi decoder. To further reduce the area of the customized Viterbi memory, common redundant hardware between the memory peripheral and computational logics is identified and eliminated without latency overhead. The 4 bit soft-decision 64-state Viterbi decoder with 24 kb eDRAM (1-bank) is implemented in 65 nm CMOS process technology. The chip measurement results show 44% area and 39% power savings over the conventional SRAM-based Viterbi decoder implementation.

KW - Application-specific memory

KW - eDRAM

KW - embedded memory

KW - gain cell

KW - reference voltage generator

KW - Viterbi decoder

UR - http://www.scopus.com/inward/record.url?scp=85027934878&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=85027934878&partnerID=8YFLogxK

U2 - 10.1109/JSSC.2015.2454241

DO - 10.1109/JSSC.2015.2454241

M3 - Article

AN - SCOPUS:85027934878

VL - 50

SP - 2451

EP - 2462

JO - IEEE Journal of Solid-State Circuits

JF - IEEE Journal of Solid-State Circuits

SN - 0018-9200

IS - 10

M1 - 7174555

ER -