A SHA-less 10-bit 80-MS/s CMOS pipelined ADC

Young Mok Jung, Jin Zhe, Chan Keun Kwon, Hoon Ki Kim, Soo Won Kim

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Citation (Scopus)

Abstract

This paper describes a 10-bit, 80MS/s CMOS pipelined Analog to Digital converter(ADC) that is implemented in a standard 180 nm technology. The ADC removes the Sample-and-Hold amplifier (SHA) to save power dissipation and die chip area. A 1.5 bit/stage architecture is used in the first stage to lower front-end. The pipelined ADC achieved a peak signal-to-noise-and-distortion ratio(SNR) of 58.2 dB, and a power consumption of 55 mW.

Original languageEnglish
Title of host publicationICSICT 2012 - 2012 IEEE 11th International Conference on Solid-State and Integrated Circuit Technology, Proceedings
DOIs
Publication statusPublished - 2012
Event2012 IEEE 11th International Conference on Solid-State and Integrated Circuit Technology, ICSICT 2012 - Xi'an, China
Duration: 2012 Oct 292012 Nov 1

Publication series

NameICSICT 2012 - 2012 IEEE 11th International Conference on Solid-State and Integrated Circuit Technology, Proceedings

Other

Other2012 IEEE 11th International Conference on Solid-State and Integrated Circuit Technology, ICSICT 2012
CountryChina
CityXi'an
Period12/10/2912/11/1

ASJC Scopus subject areas

  • Human-Computer Interaction
  • Electrical and Electronic Engineering

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  • Cite this

    Jung, Y. M., Zhe, J., Kwon, C. K., Kim, H. K., & Kim, S. W. (2012). A SHA-less 10-bit 80-MS/s CMOS pipelined ADC. In ICSICT 2012 - 2012 IEEE 11th International Conference on Solid-State and Integrated Circuit Technology, Proceedings [6467927] (ICSICT 2012 - 2012 IEEE 11th International Conference on Solid-State and Integrated Circuit Technology, Proceedings). https://doi.org/10.1109/ICSICT.2012.6467927