TY - GEN
T1 - A SHA-less 10-bit 80-MS/s CMOS pipelined ADC
AU - Jung, Young Mok
AU - Zhe, Jin
AU - Kwon, Chan Keun
AU - Kim, Hoon Ki
AU - Kim, Soo Won
PY - 2012
Y1 - 2012
N2 - This paper describes a 10-bit, 80MS/s CMOS pipelined Analog to Digital converter(ADC) that is implemented in a standard 180 nm technology. The ADC removes the Sample-and-Hold amplifier (SHA) to save power dissipation and die chip area. A 1.5 bit/stage architecture is used in the first stage to lower front-end. The pipelined ADC achieved a peak signal-to-noise-and-distortion ratio(SNR) of 58.2 dB, and a power consumption of 55 mW.
AB - This paper describes a 10-bit, 80MS/s CMOS pipelined Analog to Digital converter(ADC) that is implemented in a standard 180 nm technology. The ADC removes the Sample-and-Hold amplifier (SHA) to save power dissipation and die chip area. A 1.5 bit/stage architecture is used in the first stage to lower front-end. The pipelined ADC achieved a peak signal-to-noise-and-distortion ratio(SNR) of 58.2 dB, and a power consumption of 55 mW.
UR - http://www.scopus.com/inward/record.url?scp=84874902126&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=84874902126&partnerID=8YFLogxK
U2 - 10.1109/ICSICT.2012.6467927
DO - 10.1109/ICSICT.2012.6467927
M3 - Conference contribution
AN - SCOPUS:84874902126
SN - 9781467324724
T3 - ICSICT 2012 - 2012 IEEE 11th International Conference on Solid-State and Integrated Circuit Technology, Proceedings
BT - ICSICT 2012 - 2012 IEEE 11th International Conference on Solid-State and Integrated Circuit Technology, Proceedings
T2 - 2012 IEEE 11th International Conference on Solid-State and Integrated Circuit Technology, ICSICT 2012
Y2 - 29 October 2012 through 1 November 2012
ER -