A simple method for estimation of silicon film thickness in tri-gate junctionless transistors

Dae Young Jeon, So Jeong Park, Mireille Mouis, Sylvain Barraud, Gyu-Tae Kim, Gerard Ghibaudo

Research output: Contribution to journalArticle

Abstract

Junctionless transistors (JLTs) without PN-junctions near the source/drain (S/D) are promising candidates for further development of CMOS technology. The Si thickness (tsi) of tri-gate JLTs is crucial to understanding their unique electrical properties related to bulk neutral and surface accumulation conduction. A simple method based on a unique operation mechanism is suggested for extraction of tsi from measurements on tri-gate JLTs. The method was successfully applied to fabricated tri-gate JLTs and the extracted tsi values were comparable to those of transmission electron microscopy (TEM). Furthermore, the validity of the method was confirmed by 2D numerical simulation.

Original languageEnglish
JournalIEEE Electron Device Letters
DOIs
Publication statusAccepted/In press - 2018 Jul 18

Keywords

  • bulk neutral channel
  • junctionless transistors (JLTs)
  • method for parameter extraction
  • numerical simulation
  • Si thickness (tsi)
  • surface accumulation channel

ASJC Scopus subject areas

  • Electronic, Optical and Magnetic Materials
  • Electrical and Electronic Engineering

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