A slew-rate controlled output driver with one-cycle tuning time

Young Ho Kwaks, Inhwa Jung, Chulwoo Kim

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

A low-power slew-rate controlled output driver with open loop digital scheme, one-cycle lock time is presented. Proposed output driver maintains slew rate in the range of 2.1V/ns to 3.6V/ns in a one cycle after the enable clock is inserted. It is implemented in 0.18um CMOS process, and the control block consumes 13.7mW at 1Gbps.

Original languageEnglish
Title of host publication2008 Asia and South Pacific Design Automation Conference, ASP-DAC
Pages99-100
Number of pages2
DOIs
Publication statusPublished - 2008
Event2008 Asia and South Pacific Design Automation Conference, ASP-DAC - Seoul, Korea, Republic of
Duration: 2008 Mar 212008 Mar 24

Publication series

NameProceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC

Other

Other2008 Asia and South Pacific Design Automation Conference, ASP-DAC
CountryKorea, Republic of
CitySeoul
Period08/3/2108/3/24

ASJC Scopus subject areas

  • Computer Science Applications
  • Computer Graphics and Computer-Aided Design
  • Electrical and Electronic Engineering

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  • Cite this

    Kwaks, Y. H., Jung, I., & Kim, C. (2008). A slew-rate controlled output driver with one-cycle tuning time. In 2008 Asia and South Pacific Design Automation Conference, ASP-DAC (pp. 99-100). [4484070] (Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC). https://doi.org/10.1109/ASPDAC.2008.4484070