Abstract
Pipelined algorithms implemented in field programmable gate arrays are extensively used for hardware triggers in the modern experimental high energy physics field and the complexity of such algorithms increases rapidly. For development of such hardware triggers, algorithms are developed in C++, ported to hardware description language for synthesizing firmware, and then ported back to C++ for simulating the firmware response down to the single bit level. We present a C++ software framework which automatically simulates and generates hardware description language code for pipelined arithmetic algorithms.
| Original language | English |
|---|---|
| Pages (from-to) | 83-89 |
| Number of pages | 7 |
| Journal | Nuclear Instruments and Methods in Physics Research, Section A: Accelerators, Spectrometers, Detectors and Associated Equipment |
| Volume | 883 |
| DOIs | |
| Publication status | Published - 2018 Mar 1 |
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Keywords
- C++
- Code generation
- FPGA
- Pipelined arithmetic algorithms
- Software framework
- VHDL
ASJC Scopus subject areas
- Nuclear and High Energy Physics
- Instrumentation
Cite this
A software framework for pipelined arithmetic algorithms in field programmable gate arrays. / Kim, J. B.; Won, Eunil.
In: Nuclear Instruments and Methods in Physics Research, Section A: Accelerators, Spectrometers, Detectors and Associated Equipment, Vol. 883, 01.03.2018, p. 83-89.Research output: Contribution to journal › Article
}
TY - JOUR
T1 - A software framework for pipelined arithmetic algorithms in field programmable gate arrays
AU - Kim, J. B.
AU - Won, Eunil
PY - 2018/3/1
Y1 - 2018/3/1
N2 - Pipelined algorithms implemented in field programmable gate arrays are extensively used for hardware triggers in the modern experimental high energy physics field and the complexity of such algorithms increases rapidly. For development of such hardware triggers, algorithms are developed in C++, ported to hardware description language for synthesizing firmware, and then ported back to C++ for simulating the firmware response down to the single bit level. We present a C++ software framework which automatically simulates and generates hardware description language code for pipelined arithmetic algorithms.
AB - Pipelined algorithms implemented in field programmable gate arrays are extensively used for hardware triggers in the modern experimental high energy physics field and the complexity of such algorithms increases rapidly. For development of such hardware triggers, algorithms are developed in C++, ported to hardware description language for synthesizing firmware, and then ported back to C++ for simulating the firmware response down to the single bit level. We present a C++ software framework which automatically simulates and generates hardware description language code for pipelined arithmetic algorithms.
KW - C++
KW - Code generation
KW - FPGA
KW - Pipelined arithmetic algorithms
KW - Software framework
KW - VHDL
UR - http://www.scopus.com/inward/record.url?scp=85037548578&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=85037548578&partnerID=8YFLogxK
U2 - 10.1016/j.nima.2017.11.064
DO - 10.1016/j.nima.2017.11.064
M3 - Article
AN - SCOPUS:85037548578
VL - 883
SP - 83
EP - 89
JO - Nuclear Instruments and Methods in Physics Research, Section A: Accelerators, Spectrometers, Detectors and Associated Equipment
JF - Nuclear Instruments and Methods in Physics Research, Section A: Accelerators, Spectrometers, Detectors and Associated Equipment
SN - 0168-9002
ER -