A software framework for pipelined arithmetic algorithms in field programmable gate arrays

J. B. Kim; E. Won

doi:10.1016/j.nima.2017.11.064

A software framework for pipelined arithmetic algorithms in field programmable gate arrays

J. B. Kim, E. Won

Department of Physics

Research output: Contribution to journal › Article › peer-review

2 Citations (Scopus)

Abstract

Pipelined algorithms implemented in field programmable gate arrays are extensively used for hardware triggers in the modern experimental high energy physics field and the complexity of such algorithms increases rapidly. For development of such hardware triggers, algorithms are developed in C++, ported to hardware description language for synthesizing firmware, and then ported back to C++ for simulating the firmware response down to the single bit level. We present a C++ software framework which automatically simulates and generates hardware description language code for pipelined arithmetic algorithms.

Original language	English
Pages (from-to)	83-89
Number of pages	7
Journal	Nuclear Instruments and Methods in Physics Research, Section A: Accelerators, Spectrometers, Detectors and Associated Equipment
Volume	883
DOIs	https://doi.org/10.1016/j.nima.2017.11.064
Publication status	Published - 2018 Mar 1

Keywords

C++
Code generation
FPGA
Pipelined arithmetic algorithms
Software framework
VHDL

ASJC Scopus subject areas

Nuclear and High Energy Physics
Instrumentation

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10.1016/j.nima.2017.11.064

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title = "A software framework for pipelined arithmetic algorithms in field programmable gate arrays",

abstract = "Pipelined algorithms implemented in field programmable gate arrays are extensively used for hardware triggers in the modern experimental high energy physics field and the complexity of such algorithms increases rapidly. For development of such hardware triggers, algorithms are developed in C++, ported to hardware description language for synthesizing firmware, and then ported back to C++ for simulating the firmware response down to the single bit level. We present a C++ software framework which automatically simulates and generates hardware description language code for pipelined arithmetic algorithms.",

keywords = "C++, Code generation, FPGA, Pipelined arithmetic algorithms, Software framework, VHDL",

author = "Kim, {J. B.} and E. Won",

note = "Funding Information: We acknowledge support from the National Research Foundation of Korean Grants No. NRF-2017R1A2B3001968. Funding Information: We acknowledge support from the National Research Foundation of Korean Grants No. NRF-2017R1A2B3001968 . ",

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AU - Won, E.

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PY - 2018/3/1

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N2 - Pipelined algorithms implemented in field programmable gate arrays are extensively used for hardware triggers in the modern experimental high energy physics field and the complexity of such algorithms increases rapidly. For development of such hardware triggers, algorithms are developed in C++, ported to hardware description language for synthesizing firmware, and then ported back to C++ for simulating the firmware response down to the single bit level. We present a C++ software framework which automatically simulates and generates hardware description language code for pipelined arithmetic algorithms.

AB - Pipelined algorithms implemented in field programmable gate arrays are extensively used for hardware triggers in the modern experimental high energy physics field and the complexity of such algorithms increases rapidly. For development of such hardware triggers, algorithms are developed in C++, ported to hardware description language for synthesizing firmware, and then ported back to C++ for simulating the firmware response down to the single bit level. We present a C++ software framework which automatically simulates and generates hardware description language code for pipelined arithmetic algorithms.

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