Abstract
Pipelined algorithms implemented in field programmable gate arrays are extensively used for hardware triggers in the modern experimental high energy physics field and the complexity of such algorithms increases rapidly. For development of such hardware triggers, algorithms are developed in C++, ported to hardware description language for synthesizing firmware, and then ported back to C++ for simulating the firmware response down to the single bit level. We present a C++ software framework which automatically simulates and generates hardware description language code for pipelined arithmetic algorithms.
| Original language | English |
|---|---|
| Pages (from-to) | 83-89 |
| Number of pages | 7 |
| Journal | Nuclear Instruments and Methods in Physics Research, Section A: Accelerators, Spectrometers, Detectors and Associated Equipment |
| Volume | 883 |
| DOIs | |
| Publication status | Published - 2018 Mar 1 |
Keywords
- C++
- Code generation
- FPGA
- Pipelined arithmetic algorithms
- Software framework
- VHDL
ASJC Scopus subject areas
- Nuclear and High Energy Physics
- Instrumentation
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Cite this
Kim, J. B., & Won, E. (2018). A software framework for pipelined arithmetic algorithms in field programmable gate arrays. Nuclear Instruments and Methods in Physics Research, Section A: Accelerators, Spectrometers, Detectors and Associated Equipment, 883, 83-89. https://doi.org/10.1016/j.nima.2017.11.064