A SPICE model of p-channel silicon tunneling field-effect transistors for logic applications

Sola Woo, Juhee Jeon, Sangsig Kim

Research output: Contribution to journalArticlepeer-review

Abstract

In this study, we propose a SPICE model of p-channel silicon tunneling field-effect transistors (TFETs) for logic applications. To verify our model, electrical characteristics of fabricated p-TFETs are calibrated by utilizing TCAD and SPICE simulations. We simulate various logic gates, such as complementary TFET (c-TFET) inverters, c-TFET NAND gates, and c-TFET NOR gates using our TFET model. Our simulation shows that a c-TFET inverter can be operated at VDD as low as 0.3 V and that c-TFET logic gates based on our model can operate ~1000 times higher frequency than conventional TFET logic gates.

Original languageEnglish
Article numbere2793
JournalInternational Journal of Numerical Modelling: Electronic Networks, Devices and Fields
Volume34
Issue number1
DOIs
Publication statusPublished - 2021 Jan 1

Keywords

  • SPICE model
  • TCAD simulation
  • device modeling
  • tunnel FET
  • tunnel FET logic gate

ASJC Scopus subject areas

  • Modelling and Simulation
  • Computer Science Applications
  • Electrical and Electronic Engineering

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