A study of stress-induced p+/n salicided junction leakage failure and optimized process conditions for sub-0.15-μm CMOS technology

Joo Hyoung Lee, Sung Hyung Park, Key Min Lee, Ki Seok Youn, Young Jin Park, Chel Jong Choi, Tae Yeon Seong, Hi Deok Lee

Research output: Contribution to journalArticle

22 Citations (Scopus)

Abstract

We have clarified that mechanical stress combined with shallower junction at the active edge is the main cause of junction leakage current failure of shallow p+/n salicided junctions for sub-0.15-μm CMOS technology, especially those with narrow active width. Mechanical stress results in the penetration of a Self-Aligned siLICIDE (SALICIDE) layer at the corner region of narrow active line. Moreover, a novel electrochemical etching with TEM shows shallower junctions at the active edge due to the bending up of the junction profile. We found that the application of a shallow trench isolation (STI), top corner rounding (TCR) process suppresses the mechanical stress of STI's top corner and thus eliminates the stress-induced p+/n salicided junction leakage failure. Furthermore, we optimized the Co SALICIDE process using a Ge+ pre-amorphization in narrow p+/n salicided junction.

Original languageEnglish
Pages (from-to)1985-1992
Number of pages8
JournalIEEE Transactions on Electron Devices
Volume49
Issue number11
DOIs
Publication statusPublished - 2002 Nov
Externally publishedYes

Keywords

  • 2-D junction profile
  • Atomic force microscopy (AFM)
  • Ge pre-amorphization implant (PAI)
  • P/n salicided junction
  • SALICIDE penetration
  • Stress-induced leakage failure
  • Top corner rounding (TCR)

ASJC Scopus subject areas

  • Electronic, Optical and Magnetic Materials
  • Electrical and Electronic Engineering

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