A study of stress-induced p+/n salicided junction leakage failure and optimized process conditions for sub-0.15-μm CMOS technology

Joo Hyoung Lee; Sung Hyung Park; Key Min Lee; Ki Seok Youn; Young Jin Park; Chel Jong Choi; Tae Yeon Seong; Hi Deok Lee

doi:10.1109/TED.2002.804704

A study of stress-induced p⁺/n salicided junction leakage failure and optimized process conditions for sub-0.15-μm CMOS technology

Joo Hyoung Lee, Sung Hyung Park, Key Min Lee, Ki Seok Youn, Young Jin Park, Chel Jong Choi, Tae Yeon Seong, Hi Deok Lee

Research output: Contribution to journal › Article

22 Citations (Scopus)

Abstract

We have clarified that mechanical stress combined with shallower junction at the active edge is the main cause of junction leakage current failure of shallow p⁺/n salicided junctions for sub-0.15-μm CMOS technology, especially those with narrow active width. Mechanical stress results in the penetration of a Self-Aligned siLICIDE (SALICIDE) layer at the corner region of narrow active line. Moreover, a novel electrochemical etching with TEM shows shallower junctions at the active edge due to the bending up of the junction profile. We found that the application of a shallow trench isolation (STI), top corner rounding (TCR) process suppresses the mechanical stress of STI's top corner and thus eliminates the stress-induced p⁺/n salicided junction leakage failure. Furthermore, we optimized the Co SALICIDE process using a Ge⁺ pre-amorphization in narrow p⁺/n salicided junction.

Original language	English
Pages (from-to)	1985-1992
Number of pages	8
Journal	IEEE Transactions on Electron Devices
Volume	49
Issue number	11
DOIs	https://doi.org/10.1109/TED.2002.804704
Publication status	Published - 2002 Nov 1
Externally published	Yes

Fingerprint

p-n junctions

CMOS

leakage

combined stress

Electrochemical etching

Amorphization

Leakage currents

isolation

penetration

etching

Transmission electron microscopy

transmission electron microscopy

causes

profiles

Keywords

2-D junction profile
Atomic force microscopy (AFM)
Ge pre-amorphization implant (PAI)
P/n salicided junction
SALICIDE penetration
Stress-induced leakage failure
Top corner rounding (TCR)

ASJC Scopus subject areas

Electrical and Electronic Engineering
Physics and Astronomy (miscellaneous)

Cite this

Lee, J. H., Park, S. H., Lee, K. M., Youn, K. S., Park, Y. J., Choi, C. J., ... Lee, H. D. (2002). A study of stress-induced p⁺/n salicided junction leakage failure and optimized process conditions for sub-0.15-μm CMOS technology. IEEE Transactions on Electron Devices, 49(11), 1985-1992. https://doi.org/10.1109/TED.2002.804704

A study of stress-induced p⁺/n salicided junction leakage failure and optimized process conditions for sub-0.15-μm CMOS technology. / Lee, Joo Hyoung; Park, Sung Hyung; Lee, Key Min; Youn, Ki Seok; Park, Young Jin; Choi, Chel Jong; Seong, Tae Yeon; Lee, Hi Deok.

In: IEEE Transactions on Electron Devices, Vol. 49, No. 11, 01.11.2002, p. 1985-1992.

Research output: Contribution to journal › Article

Lee, JH, Park, SH, Lee, KM, Youn, KS, Park, YJ, Choi, CJ, Seong, TY & Lee, HD 2002, 'A study of stress-induced p⁺/n salicided junction leakage failure and optimized process conditions for sub-0.15-μm CMOS technology', IEEE Transactions on Electron Devices, vol. 49, no. 11, pp. 1985-1992. https://doi.org/10.1109/TED.2002.804704

Lee JH, Park SH, Lee KM, Youn KS, Park YJ, Choi CJ et al. A study of stress-induced p⁺/n salicided junction leakage failure and optimized process conditions for sub-0.15-μm CMOS technology. IEEE Transactions on Electron Devices. 2002 Nov 1;49(11):1985-1992. https://doi.org/10.1109/TED.2002.804704

Lee, Joo Hyoung ; Park, Sung Hyung ; Lee, Key Min ; Youn, Ki Seok ; Park, Young Jin ; Choi, Chel Jong ; Seong, Tae Yeon ; Lee, Hi Deok. / A study of stress-induced p⁺/n salicided junction leakage failure and optimized process conditions for sub-0.15-μm CMOS technology. In: IEEE Transactions on Electron Devices. 2002 ; Vol. 49, No. 11. pp. 1985-1992.

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abstract = "We have clarified that mechanical stress combined with shallower junction at the active edge is the main cause of junction leakage current failure of shallow p+/n salicided junctions for sub-0.15-μm CMOS technology, especially those with narrow active width. Mechanical stress results in the penetration of a Self-Aligned siLICIDE (SALICIDE) layer at the corner region of narrow active line. Moreover, a novel electrochemical etching with TEM shows shallower junctions at the active edge due to the bending up of the junction profile. We found that the application of a shallow trench isolation (STI), top corner rounding (TCR) process suppresses the mechanical stress of STI's top corner and thus eliminates the stress-induced p+/n salicided junction leakage failure. Furthermore, we optimized the Co SALICIDE process using a Ge+ pre-amorphization in narrow p+/n salicided junction.",

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AU - Choi, Chel Jong

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N2 - We have clarified that mechanical stress combined with shallower junction at the active edge is the main cause of junction leakage current failure of shallow p+/n salicided junctions for sub-0.15-μm CMOS technology, especially those with narrow active width. Mechanical stress results in the penetration of a Self-Aligned siLICIDE (SALICIDE) layer at the corner region of narrow active line. Moreover, a novel electrochemical etching with TEM shows shallower junctions at the active edge due to the bending up of the junction profile. We found that the application of a shallow trench isolation (STI), top corner rounding (TCR) process suppresses the mechanical stress of STI's top corner and thus eliminates the stress-induced p+/n salicided junction leakage failure. Furthermore, we optimized the Co SALICIDE process using a Ge+ pre-amorphization in narrow p+/n salicided junction.

AB - We have clarified that mechanical stress combined with shallower junction at the active edge is the main cause of junction leakage current failure of shallow p+/n salicided junctions for sub-0.15-μm CMOS technology, especially those with narrow active width. Mechanical stress results in the penetration of a Self-Aligned siLICIDE (SALICIDE) layer at the corner region of narrow active line. Moreover, a novel electrochemical etching with TEM shows shallower junctions at the active edge due to the bending up of the junction profile. We found that the application of a shallow trench isolation (STI), top corner rounding (TCR) process suppresses the mechanical stress of STI's top corner and thus eliminates the stress-induced p+/n salicided junction leakage failure. Furthermore, we optimized the Co SALICIDE process using a Ge+ pre-amorphization in narrow p+/n salicided junction.

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Access to Document

10.1109/TED.2002.804704