A Sub-fs-FoM Digital LDO Using PMOS and NMOS Arrays with Fully Integrated 7.2-pF Total Capacitance

Junyoung Maeng, Minseob Shim, Junwon Jeong, Inho Park, Yunsoo Park, Chulwoo Kim

Research output: Contribution to journalArticle

Abstract

A digital low-dropout (DLDO) regulator using p-type MOS (PMOS) and n-type MOS (NMOS) switches is proposed to achieve a sub-fs speed figure-of-merit (FoM) by reducing the total capacitance ( C_{\mathrm {TOT}} ) and accomplishing a comparable output voltage droop ( \Delta V_{\mathrm {OUT}} ) during a load transition. The proposed DLDO uses the segmented PMOS switches to fully turn on the NMOS array, which strengthens the intrinsic NMOS loop and maintains the undershoot and overshoot voltages of 88 and 42 mV, respectively, during an 88.4-mA load transition. In addition, with the aid of the proposed voltage doubler (VD)-based periodically refreshed level shifter (PRLS), the total capacitance of DLDO to drive NMOS array is reduced to 7.2 pF, which is 3.3 \times smaller than that of previous work, extending the input voltage ( V_{\mathrm {IN}} ) and load current ( I_{\mathrm {LOAD}} ) ranges up to 0.9 V and 140 mA, respectively. The proposed DLDO is fabricated using a 28-nm CMOS process and achieves a 0.12-fs speed FoM that is 42.5 \times smaller than the state-of-the-art designs.

Original languageEnglish
Article number8905784
Pages (from-to)1624-1636
Number of pages13
JournalIEEE Journal of Solid-State Circuits
Volume55
Issue number6
DOIs
Publication statusPublished - 2020 Jun

Keywords

  • Capacitively coupled level shifter (CCLS)
  • digital low-dropout (DLDO) regulator
  • fully integrated voltage regulator
  • periodic charge refresh
  • power management

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

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