Abstract
We propose a subtraction-based adder amplifier to be used to implement high-speed and low-power pipelined-ADC's which are employed for high-speed signal processing, i. e. image processing. Proposed amplifier, to be used as a residue amplifier, consumes low-power and occupies small area. We analyzed the amplifier and designed a 1-bit stage of a 10b 50MS/s pipelined analog-to-digital converter.
| Original language | English |
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| Title of host publication | Midwest Symposium on Circuits and Systems |
| Volume | 1 |
| Publication status | Published - 2004 |
| Event | The 2004 47th Midwest Symposium on Circuits and Systems - Conference Proceedings - Hiroshima, Japan Duration: 2004 Jul 25 → 2004 Jul 28 |
Other
| Other | The 2004 47th Midwest Symposium on Circuits and Systems - Conference Proceedings |
|---|---|
| Country | Japan |
| City | Hiroshima |
| Period | 04/7/25 → 04/7/28 |
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ASJC Scopus subject areas
- Electrical and Electronic Engineering
- Electronic, Optical and Magnetic Materials
Cite this
Kim, G. S., Ki, H. J., Kim, S-W., & Yoo, J. T. (2004). A subtraction-based adder amplifier for 10b 50MS/s low-power pipelined-ADC's. In Midwest Symposium on Circuits and Systems (Vol. 1)