A subtraction-based adder amplifier for 10b 50MS/s low-power pipelined-ADC's

Gil Su Kim, Hoon Jae Ki, Soo Won Kim, Jae Tack Yoo

Research output: Contribution to journalConference article

Abstract

We propose a subtraction-based adder amplifier to be used to implement high-speed and low-power pipelined-ADC's which are employed for high-speed signal processing, i. e. image processing. Proposed amplifier, to be used as a residue amplifier, consumes low-power and occupies small area. We analyzed the amplifier and designed a 1-bit stage of a 10b 50MS/s pipelined analog-to-digital converter.

Original languageEnglish
Pages (from-to)I333-I336
JournalMidwest Symposium on Circuits and Systems
Volume1
Publication statusPublished - 2004
EventThe 2004 47th Midwest Symposium on Circuits and Systems - Conference Proceedings - Hiroshima, Japan
Duration: 2004 Jul 252004 Jul 28

ASJC Scopus subject areas

  • Electronic, Optical and Magnetic Materials
  • Electrical and Electronic Engineering

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