A subtraction-based adder amplifier for 10b 50MS/s low-power pipelined-ADC's

Gil S. Kim, Hoon Jae Ki, Soo-Won Kim, Jae Tack Yoo

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

We propose a subtraction-based adder amplifier to be used to implement high-speed and low-power pipelined-ADC's which are employed for high-speed signal processing, i. e. image processing. Proposed amplifier, to be used as a residue amplifier, consumes low-power and occupies small area. We analyzed the amplifier and designed a 1-bit stage of a 10b 50MS/s pipelined analog-to-digital converter.

Original languageEnglish
Title of host publicationMidwest Symposium on Circuits and Systems
Volume1
Publication statusPublished - 2004
EventThe 2004 47th Midwest Symposium on Circuits and Systems - Conference Proceedings - Hiroshima, Japan
Duration: 2004 Jul 252004 Jul 28

Other

OtherThe 2004 47th Midwest Symposium on Circuits and Systems - Conference Proceedings
CountryJapan
CityHiroshima
Period04/7/2504/7/28

Fingerprint

Adders
Digital to analog conversion
Signal processing
Image processing

ASJC Scopus subject areas

  • Electrical and Electronic Engineering
  • Electronic, Optical and Magnetic Materials

Cite this

Kim, G. S., Ki, H. J., Kim, S-W., & Yoo, J. T. (2004). A subtraction-based adder amplifier for 10b 50MS/s low-power pipelined-ADC's. In Midwest Symposium on Circuits and Systems (Vol. 1)

A subtraction-based adder amplifier for 10b 50MS/s low-power pipelined-ADC's. / Kim, Gil S.; Ki, Hoon Jae; Kim, Soo-Won; Yoo, Jae Tack.

Midwest Symposium on Circuits and Systems. Vol. 1 2004.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Kim, GS, Ki, HJ, Kim, S-W & Yoo, JT 2004, A subtraction-based adder amplifier for 10b 50MS/s low-power pipelined-ADC's. in Midwest Symposium on Circuits and Systems. vol. 1, The 2004 47th Midwest Symposium on Circuits and Systems - Conference Proceedings, Hiroshima, Japan, 04/7/25.
Kim GS, Ki HJ, Kim S-W, Yoo JT. A subtraction-based adder amplifier for 10b 50MS/s low-power pipelined-ADC's. In Midwest Symposium on Circuits and Systems. Vol. 1. 2004
Kim, Gil S. ; Ki, Hoon Jae ; Kim, Soo-Won ; Yoo, Jae Tack. / A subtraction-based adder amplifier for 10b 50MS/s low-power pipelined-ADC's. Midwest Symposium on Circuits and Systems. Vol. 1 2004.
@inproceedings{49db9c321f0d482598b6e977a676e0b2,
title = "A subtraction-based adder amplifier for 10b 50MS/s low-power pipelined-ADC's",
abstract = "We propose a subtraction-based adder amplifier to be used to implement high-speed and low-power pipelined-ADC's which are employed for high-speed signal processing, i. e. image processing. Proposed amplifier, to be used as a residue amplifier, consumes low-power and occupies small area. We analyzed the amplifier and designed a 1-bit stage of a 10b 50MS/s pipelined analog-to-digital converter.",
author = "Kim, {Gil S.} and Ki, {Hoon Jae} and Soo-Won Kim and Yoo, {Jae Tack}",
year = "2004",
language = "English",
volume = "1",
booktitle = "Midwest Symposium on Circuits and Systems",

}

TY - GEN

T1 - A subtraction-based adder amplifier for 10b 50MS/s low-power pipelined-ADC's

AU - Kim, Gil S.

AU - Ki, Hoon Jae

AU - Kim, Soo-Won

AU - Yoo, Jae Tack

PY - 2004

Y1 - 2004

N2 - We propose a subtraction-based adder amplifier to be used to implement high-speed and low-power pipelined-ADC's which are employed for high-speed signal processing, i. e. image processing. Proposed amplifier, to be used as a residue amplifier, consumes low-power and occupies small area. We analyzed the amplifier and designed a 1-bit stage of a 10b 50MS/s pipelined analog-to-digital converter.

AB - We propose a subtraction-based adder amplifier to be used to implement high-speed and low-power pipelined-ADC's which are employed for high-speed signal processing, i. e. image processing. Proposed amplifier, to be used as a residue amplifier, consumes low-power and occupies small area. We analyzed the amplifier and designed a 1-bit stage of a 10b 50MS/s pipelined analog-to-digital converter.

UR - http://www.scopus.com/inward/record.url?scp=11144232921&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=11144232921&partnerID=8YFLogxK

M3 - Conference contribution

AN - SCOPUS:11144232921

VL - 1

BT - Midwest Symposium on Circuits and Systems

ER -