We propose a subtraction-based adder amplifier to be used to implement high-speed and low-power pipelined-ADC's which are employed for high-speed signal processing, i. e. image processing. Proposed amplifier, to be used as a residue amplifier, consumes low-power and occupies small area. We analyzed the amplifier and designed a 1-bit stage of a 10b 50MS/s pipelined analog-to-digital converter.
|Journal||Midwest Symposium on Circuits and Systems|
|Publication status||Published - 2004|
|Event||The 2004 47th Midwest Symposium on Circuits and Systems - Conference Proceedings - Hiroshima, Japan|
Duration: 2004 Jul 25 → 2004 Jul 28
ASJC Scopus subject areas
- Electronic, Optical and Magnetic Materials
- Electrical and Electronic Engineering