A subtraction-based adder amplifier for 10b 50MS/s low-power pipelined-ADC's

Gil Su Kim; Hoon Jae Ki; Soo Won Kim; Jae Tack Yoo

A subtraction-based adder amplifier for 10b 50MS/s low-power pipelined-ADC's

Gil Su Kim, Hoon Jae Ki, Soo Won Kim, Jae Tack Yoo

Honorary professors

Research output: Contribution to journal › Conference article › peer-review

Abstract

We propose a subtraction-based adder amplifier to be used to implement high-speed and low-power pipelined-ADC's which are employed for high-speed signal processing, i. e. image processing. Proposed amplifier, to be used as a residue amplifier, consumes low-power and occupies small area. We analyzed the amplifier and designed a 1-bit stage of a 10b 50MS/s pipelined analog-to-digital converter.

Original language	English
Pages (from-to)	I333-I336
Journal	Midwest Symposium on Circuits and Systems
Volume	1
Publication status	Published - 2004
Event	The 2004 47th Midwest Symposium on Circuits and Systems - Conference Proceedings - Hiroshima, Japan Duration: 2004 Jul 25 → 2004 Jul 28

ASJC Scopus subject areas

Electronic, Optical and Magnetic Materials
Electrical and Electronic Engineering

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abstract = "We propose a subtraction-based adder amplifier to be used to implement high-speed and low-power pipelined-ADC's which are employed for high-speed signal processing, i. e. image processing. Proposed amplifier, to be used as a residue amplifier, consumes low-power and occupies small area. We analyzed the amplifier and designed a 1-bit stage of a 10b 50MS/s pipelined analog-to-digital converter.",

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AU - Kim, Gil Su

AU - Ki, Hoon Jae

AU - Kim, Soo Won

AU - Yoo, Jae Tack

PY - 2004

Y1 - 2004

N2 - We propose a subtraction-based adder amplifier to be used to implement high-speed and low-power pipelined-ADC's which are employed for high-speed signal processing, i. e. image processing. Proposed amplifier, to be used as a residue amplifier, consumes low-power and occupies small area. We analyzed the amplifier and designed a 1-bit stage of a 10b 50MS/s pipelined analog-to-digital converter.

AB - We propose a subtraction-based adder amplifier to be used to implement high-speed and low-power pipelined-ADC's which are employed for high-speed signal processing, i. e. image processing. Proposed amplifier, to be used as a residue amplifier, consumes low-power and occupies small area. We analyzed the amplifier and designed a 1-bit stage of a 10b 50MS/s pipelined analog-to-digital converter.

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M3 - Conference article

AN - SCOPUS:11144232921

VL - 1

SP - I333-I336

JO - Midwest Symposium on Circuits and Systems

JF - Midwest Symposium on Circuits and Systems

SN - 1548-3746

T2 - The 2004 47th Midwest Symposium on Circuits and Systems - Conference Proceedings

Y2 - 25 July 2004 through 28 July 2004

ER -

A subtraction-based adder amplifier for 10b 50MS/s low-power pipelined-ADC's

Abstract

ASJC Scopus subject areas

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