### Abstract

This paper proposed a synchronous PWM method of parallel AC-DC converters. The parallel AC-DC converters of traction control system for high speed train require accurate PLL (Phase-Locked Logic) method and synchronous PWM algorithm with phase delay control to implement unit power factor and input current harmonic reduction. The phase delay control of parallel converters driven by individual controllers is difficult. The proposed hybrid PLL algorithm detects the input voltage phase angle more accurately and improves the performance of phase delay control. The hybrid PLL algorithm consists of two kinds of method which calculate simultaneously the phase angle of input voltage. The single-phase AC-DC converters are connected in parallel through main transformer. The first PLL algorithm calculates the phase angle of primary input voltage adopting the digital APF (All-Pass Filter) and it has robust characteristics against the disturbance of input signal compared with conventional zero-crossing detection method by hardware circuit. The estimated phase angle of this algorithm is used for unit power factor control and instantaneous input current control. The second PLL algorithm generates the common reference signal for synchronous PWM by measuring the amplitude of input voltage at the near zero-crossing point. This paper describes the implementation of hybrid PLL algorithm adopting two different kinds of PLL method in detail. The feasibility of this algorithm is proven by experimental study on parallel converters (1.25MW×4) for high speed train.

Original language | English |
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Title of host publication | IECON Proceedings (Industrial Electronics Conference) |

Pages | 1161-1166 |

Number of pages | 6 |

DOIs | |

Publication status | Published - 2011 Dec 1 |

Event | 37th Annual Conference of the IEEE Industrial Electronics Society, IECON 2011 - Melbourne, VIC, Australia Duration: 2011 Nov 7 → 2011 Nov 10 |

### Other

Other | 37th Annual Conference of the IEEE Industrial Electronics Society, IECON 2011 |
---|---|

Country | Australia |

City | Melbourne, VIC |

Period | 11/11/7 → 11/11/10 |

### Fingerprint

### ASJC Scopus subject areas

- Control and Systems Engineering
- Electrical and Electronic Engineering

### Cite this

*IECON Proceedings (Industrial Electronics Conference)*(pp. 1161-1166). [6119472] https://doi.org/10.1109/IECON.2011.6119472

**A synchronous PWM method of parallel AC-DC converters using hybrid-PLL algorithm.** / Cho, Sung Joon; Lee, Kwang Hwan; Jeong, Man Kyu; Yoo, Ji Yoon.

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

*IECON Proceedings (Industrial Electronics Conference).*, 6119472, pp. 1161-1166, 37th Annual Conference of the IEEE Industrial Electronics Society, IECON 2011, Melbourne, VIC, Australia, 11/11/7. https://doi.org/10.1109/IECON.2011.6119472

}

TY - GEN

T1 - A synchronous PWM method of parallel AC-DC converters using hybrid-PLL algorithm

AU - Cho, Sung Joon

AU - Lee, Kwang Hwan

AU - Jeong, Man Kyu

AU - Yoo, Ji Yoon

PY - 2011/12/1

Y1 - 2011/12/1

N2 - This paper proposed a synchronous PWM method of parallel AC-DC converters. The parallel AC-DC converters of traction control system for high speed train require accurate PLL (Phase-Locked Logic) method and synchronous PWM algorithm with phase delay control to implement unit power factor and input current harmonic reduction. The phase delay control of parallel converters driven by individual controllers is difficult. The proposed hybrid PLL algorithm detects the input voltage phase angle more accurately and improves the performance of phase delay control. The hybrid PLL algorithm consists of two kinds of method which calculate simultaneously the phase angle of input voltage. The single-phase AC-DC converters are connected in parallel through main transformer. The first PLL algorithm calculates the phase angle of primary input voltage adopting the digital APF (All-Pass Filter) and it has robust characteristics against the disturbance of input signal compared with conventional zero-crossing detection method by hardware circuit. The estimated phase angle of this algorithm is used for unit power factor control and instantaneous input current control. The second PLL algorithm generates the common reference signal for synchronous PWM by measuring the amplitude of input voltage at the near zero-crossing point. This paper describes the implementation of hybrid PLL algorithm adopting two different kinds of PLL method in detail. The feasibility of this algorithm is proven by experimental study on parallel converters (1.25MW×4) for high speed train.

AB - This paper proposed a synchronous PWM method of parallel AC-DC converters. The parallel AC-DC converters of traction control system for high speed train require accurate PLL (Phase-Locked Logic) method and synchronous PWM algorithm with phase delay control to implement unit power factor and input current harmonic reduction. The phase delay control of parallel converters driven by individual controllers is difficult. The proposed hybrid PLL algorithm detects the input voltage phase angle more accurately and improves the performance of phase delay control. The hybrid PLL algorithm consists of two kinds of method which calculate simultaneously the phase angle of input voltage. The single-phase AC-DC converters are connected in parallel through main transformer. The first PLL algorithm calculates the phase angle of primary input voltage adopting the digital APF (All-Pass Filter) and it has robust characteristics against the disturbance of input signal compared with conventional zero-crossing detection method by hardware circuit. The estimated phase angle of this algorithm is used for unit power factor control and instantaneous input current control. The second PLL algorithm generates the common reference signal for synchronous PWM by measuring the amplitude of input voltage at the near zero-crossing point. This paper describes the implementation of hybrid PLL algorithm adopting two different kinds of PLL method in detail. The feasibility of this algorithm is proven by experimental study on parallel converters (1.25MW×4) for high speed train.

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U2 - 10.1109/IECON.2011.6119472

DO - 10.1109/IECON.2011.6119472

M3 - Conference contribution

AN - SCOPUS:84863062070

SN - 9781612849720

SP - 1161

EP - 1166

BT - IECON Proceedings (Industrial Electronics Conference)

ER -