A time-to-digital converter (TDC)-based skew compensation technique is proposed to minimize timing skew between main and pre-emphasis signals of high-speed current mode output driver. Skew between signals of main and pre-emphasis branches of output driver increases jitter. The proposed technique measures and compensates the timing skew to reduce the jitter in the output data. With the compensation technique, maximum jitter reduction achieved is as high as 49%. The power overhead for the compensation block is only 7% of the total power consumption. The output driver with the proposed compensation technique is designed using 110 nm CMOS process technology.