A two-step folder for a high-speed CMOS folding-and-interpolating ADC

Sang Chan Han, Bum Soo Suh, Soo Won Kim

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

Optimum design flow of a two-step folder for the input-bandwidth extension of a CMOS folding-and-interpolating ADC is presented. We derived the minimum transistor sizes of the two-step folder and analyzed the effects of the offset voltage. We implemented a folding-and-interpolating ADC adopting the two-step folder in a 0.25 μm 1P-5M CMOS process and got an experimental result of the input bandwidth of 50 MHz. This result verifies the design flow.

Original languageEnglish
Title of host publicationICECS 2001 - 8th IEEE International Conference on Electronics, Circuits and Systems
Pages325-328
Number of pages4
Publication statusPublished - 2001
Event8th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2001 - , Malta
Duration: 2001 Sep 22001 Sep 5

Publication series

NameProceedings of the IEEE International Conference on Electronics, Circuits, and Systems
Volume1

Other

Other8th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2001
CountryMalta
Period01/9/201/9/5

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

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  • Cite this

    Han, S. C., Suh, B. S., & Kim, S. W. (2001). A two-step folder for a high-speed CMOS folding-and-interpolating ADC. In ICECS 2001 - 8th IEEE International Conference on Electronics, Circuits and Systems (pp. 325-328). [957745] (Proceedings of the IEEE International Conference on Electronics, Circuits, and Systems; Vol. 1).