A two-step folder for a high-speed CMOS folding-and-interpolating ADC

Sang Chan Han, Bum Soo Suh, Soo-Won Kim

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

Optimum design flow of a two-step folder for the input-bandwidth extension of a CMOS folding-and-interpolating ADC is presented. We derived the minimum transistor sizes of the two-step folder and analyzed the effects of the offset voltage. We implemented a folding-and-interpolating ADC adopting the two-step folder in a 0.25 μm 1P-5M CMOS process and got an experimental result of the input bandwidth of 50 MHz. This result verifies the design flow.

Original languageEnglish
Title of host publicationProceedings of the IEEE International Conference on Electronics, Circuits, and Systems
Pages325-328
Number of pages4
Volume1
Publication statusPublished - 2001 Dec 1
Event8th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2001 - , Malta
Duration: 2001 Sep 22001 Sep 5

Other

Other8th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2001
CountryMalta
Period01/9/201/9/5

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Bandwidth
Transistors
Electric potential
Optimum design

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

Cite this

Han, S. C., Suh, B. S., & Kim, S-W. (2001). A two-step folder for a high-speed CMOS folding-and-interpolating ADC. In Proceedings of the IEEE International Conference on Electronics, Circuits, and Systems (Vol. 1, pp. 325-328). [957745]

A two-step folder for a high-speed CMOS folding-and-interpolating ADC. / Han, Sang Chan; Suh, Bum Soo; Kim, Soo-Won.

Proceedings of the IEEE International Conference on Electronics, Circuits, and Systems. Vol. 1 2001. p. 325-328 957745.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Han, SC, Suh, BS & Kim, S-W 2001, A two-step folder for a high-speed CMOS folding-and-interpolating ADC. in Proceedings of the IEEE International Conference on Electronics, Circuits, and Systems. vol. 1, 957745, pp. 325-328, 8th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2001, Malta, 01/9/2.
Han SC, Suh BS, Kim S-W. A two-step folder for a high-speed CMOS folding-and-interpolating ADC. In Proceedings of the IEEE International Conference on Electronics, Circuits, and Systems. Vol. 1. 2001. p. 325-328. 957745
Han, Sang Chan ; Suh, Bum Soo ; Kim, Soo-Won. / A two-step folder for a high-speed CMOS folding-and-interpolating ADC. Proceedings of the IEEE International Conference on Electronics, Circuits, and Systems. Vol. 1 2001. pp. 325-328
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