A wide-range all-digital multiphase DLL with supply noise tolerance

Hyunsoo Chae, Dongsuk Shin, Kisoo Kim, Kwan Weon Kim, Young Jung Choi, Chulwoo Kim

Research output: Chapter in Book/Report/Conference proceedingConference contribution

6 Citations (Scopus)

Abstract

An 80-to-832MHz all-digital 8-differential-phase DLL in a 0.18um CMOS process has been developed to achieve low-jitter and supply noise tolerance using dual window phase detector, noise tolerant delay cell and delay compensation under supply noise. The proposed DLL occupies 0.19mm2 and dissipates 48mW at 832MHz from a 1.8V supply. The peak-to-peak jitter and rms jitter are 12ps and 1.73ps with a quiet supply at 832MHz, respectively. The peak-to-peak and rms jitter with a 100mV peak-to-peak triangular supply noise at 100MHz are 21ps and 2.99ps, respectively.

Original languageEnglish
Title of host publicationProceedings of 2008 IEEE Asian Solid-State Circuits Conference, A-SSCC 2008
Pages421-424
Number of pages4
DOIs
Publication statusPublished - 2008 Dec 1
Event2008 IEEE Asian Solid-State Circuits Conference, A-SSCC 2008 - Fukuoka, Japan
Duration: 2008 Nov 32008 Nov 5

Publication series

NameProceedings of 2008 IEEE Asian Solid-State Circuits Conference, A-SSCC 2008

Other

Other2008 IEEE Asian Solid-State Circuits Conference, A-SSCC 2008
CountryJapan
CityFukuoka
Period08/11/308/11/5

ASJC Scopus subject areas

  • Hardware and Architecture
  • Electrical and Electronic Engineering

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    Chae, H., Shin, D., Kim, K., Kim, K. W., Choi, Y. J., & Kim, C. (2008). A wide-range all-digital multiphase DLL with supply noise tolerance. In Proceedings of 2008 IEEE Asian Solid-State Circuits Conference, A-SSCC 2008 (pp. 421-424). [4708817] (Proceedings of 2008 IEEE Asian Solid-State Circuits Conference, A-SSCC 2008). https://doi.org/10.1109/ASSCC.2008.4708817