Adaptive clock generation technique for variation-aware subthreshold logics

Woojin Rim, Woong Choi, Jongsun Park

Research output: Contribution to journalArticle

6 Citations (Scopus)

Abstract

Subthreshold logic has become an attractive option in energy-constrained applications, where the key metric is energy consumption rather than operating speed or silicon area. However, the performance of circuits operating in the subthreshold region is extremely sensitive to the variations in the process, supply voltage, and temperature (PVT). Generally, circuit designers increase the clock period in order to reduce the timing failures, as well as to ensure the correct operations under all PVT conditions. However, increasing the clock period up to the worst-case critical path delay incurs a significant increase in the active leakage energy. This brief presents an adaptive clock generation scheme for subthreshold logics, wherein a replica module inside measures the variations and helps generate a clock with the correct period. As a result, considerable energy savings is achieved, along with a reduction in the setup time violations. The experimental results obtained with a 0.13-μm CMOS process show that the proposed scheme achieves energy savings of up to 63.8% with the selection of four different clock cycles under a supply voltage of 0.3 V.

Original languageEnglish
Article number6247477
Pages (from-to)587-591
Number of pages5
JournalIEEE Transactions on Circuits and Systems II: Express Briefs
Volume59
Issue number9
DOIs
Publication statusPublished - 2012 Aug 1

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Clocks
Energy conservation
Electric potential
Networks (circuits)
Energy utilization
Silicon
Temperature

Keywords

  • Active leakage energy
  • subthreshold logics
  • ultralow voltage

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

Cite this

Adaptive clock generation technique for variation-aware subthreshold logics. / Rim, Woojin; Choi, Woong; Park, Jongsun.

In: IEEE Transactions on Circuits and Systems II: Express Briefs, Vol. 59, No. 9, 6247477, 01.08.2012, p. 587-591.

Research output: Contribution to journalArticle

@article{575dee0b1ecc490f97f7b2f85315ee69,
title = "Adaptive clock generation technique for variation-aware subthreshold logics",
abstract = "Subthreshold logic has become an attractive option in energy-constrained applications, where the key metric is energy consumption rather than operating speed or silicon area. However, the performance of circuits operating in the subthreshold region is extremely sensitive to the variations in the process, supply voltage, and temperature (PVT). Generally, circuit designers increase the clock period in order to reduce the timing failures, as well as to ensure the correct operations under all PVT conditions. However, increasing the clock period up to the worst-case critical path delay incurs a significant increase in the active leakage energy. This brief presents an adaptive clock generation scheme for subthreshold logics, wherein a replica module inside measures the variations and helps generate a clock with the correct period. As a result, considerable energy savings is achieved, along with a reduction in the setup time violations. The experimental results obtained with a 0.13-μm CMOS process show that the proposed scheme achieves energy savings of up to 63.8{\%} with the selection of four different clock cycles under a supply voltage of 0.3 V.",
keywords = "Active leakage energy, subthreshold logics, ultralow voltage",
author = "Woojin Rim and Woong Choi and Jongsun Park",
year = "2012",
month = "8",
day = "1",
doi = "10.1109/TCSII.2012.2206933",
language = "English",
volume = "59",
pages = "587--591",
journal = "IEEE Transactions on Circuits and Systems I: Regular Papers",
issn = "1549-8328",
publisher = "Institute of Electrical and Electronics Engineers Inc.",
number = "9",

}

TY - JOUR

T1 - Adaptive clock generation technique for variation-aware subthreshold logics

AU - Rim, Woojin

AU - Choi, Woong

AU - Park, Jongsun

PY - 2012/8/1

Y1 - 2012/8/1

N2 - Subthreshold logic has become an attractive option in energy-constrained applications, where the key metric is energy consumption rather than operating speed or silicon area. However, the performance of circuits operating in the subthreshold region is extremely sensitive to the variations in the process, supply voltage, and temperature (PVT). Generally, circuit designers increase the clock period in order to reduce the timing failures, as well as to ensure the correct operations under all PVT conditions. However, increasing the clock period up to the worst-case critical path delay incurs a significant increase in the active leakage energy. This brief presents an adaptive clock generation scheme for subthreshold logics, wherein a replica module inside measures the variations and helps generate a clock with the correct period. As a result, considerable energy savings is achieved, along with a reduction in the setup time violations. The experimental results obtained with a 0.13-μm CMOS process show that the proposed scheme achieves energy savings of up to 63.8% with the selection of four different clock cycles under a supply voltage of 0.3 V.

AB - Subthreshold logic has become an attractive option in energy-constrained applications, where the key metric is energy consumption rather than operating speed or silicon area. However, the performance of circuits operating in the subthreshold region is extremely sensitive to the variations in the process, supply voltage, and temperature (PVT). Generally, circuit designers increase the clock period in order to reduce the timing failures, as well as to ensure the correct operations under all PVT conditions. However, increasing the clock period up to the worst-case critical path delay incurs a significant increase in the active leakage energy. This brief presents an adaptive clock generation scheme for subthreshold logics, wherein a replica module inside measures the variations and helps generate a clock with the correct period. As a result, considerable energy savings is achieved, along with a reduction in the setup time violations. The experimental results obtained with a 0.13-μm CMOS process show that the proposed scheme achieves energy savings of up to 63.8% with the selection of four different clock cycles under a supply voltage of 0.3 V.

KW - Active leakage energy

KW - subthreshold logics

KW - ultralow voltage

UR - http://www.scopus.com/inward/record.url?scp=84866480846&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=84866480846&partnerID=8YFLogxK

U2 - 10.1109/TCSII.2012.2206933

DO - 10.1109/TCSII.2012.2206933

M3 - Article

VL - 59

SP - 587

EP - 591

JO - IEEE Transactions on Circuits and Systems I: Regular Papers

JF - IEEE Transactions on Circuits and Systems I: Regular Papers

SN - 1549-8328

IS - 9

M1 - 6247477

ER -