Abstract
Subthreshold logic has become an attractive option in energy-constrained applications, where the key metric is energy consumption rather than operating speed or silicon area. However, the performance of circuits operating in the subthreshold region is extremely sensitive to the variations in the process, supply voltage, and temperature (PVT). Generally, circuit designers increase the clock period in order to reduce the timing failures, as well as to ensure the correct operations under all PVT conditions. However, increasing the clock period up to the worst-case critical path delay incurs a significant increase in the active leakage energy. This brief presents an adaptive clock generation scheme for subthreshold logics, wherein a replica module inside measures the variations and helps generate a clock with the correct period. As a result, considerable energy savings is achieved, along with a reduction in the setup time violations. The experimental results obtained with a 0.13-μm CMOS process show that the proposed scheme achieves energy savings of up to 63.8% with the selection of four different clock cycles under a supply voltage of 0.3 V.
| Original language | English |
|---|---|
| Article number | 6247477 |
| Pages (from-to) | 587-591 |
| Number of pages | 5 |
| Journal | IEEE Transactions on Circuits and Systems II: Express Briefs |
| Volume | 59 |
| Issue number | 9 |
| DOIs | |
| Publication status | Published - 2012 Aug 1 |
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Keywords
- Active leakage energy
- subthreshold logics
- ultralow voltage
ASJC Scopus subject areas
- Electrical and Electronic Engineering
Cite this
Adaptive clock generation technique for variation-aware subthreshold logics. / Rim, Woojin; Choi, Woong; Park, Jongsun.
In: IEEE Transactions on Circuits and Systems II: Express Briefs, Vol. 59, No. 9, 6247477, 01.08.2012, p. 587-591.Research output: Contribution to journal › Article
}
TY - JOUR
T1 - Adaptive clock generation technique for variation-aware subthreshold logics
AU - Rim, Woojin
AU - Choi, Woong
AU - Park, Jongsun
PY - 2012/8/1
Y1 - 2012/8/1
N2 - Subthreshold logic has become an attractive option in energy-constrained applications, where the key metric is energy consumption rather than operating speed or silicon area. However, the performance of circuits operating in the subthreshold region is extremely sensitive to the variations in the process, supply voltage, and temperature (PVT). Generally, circuit designers increase the clock period in order to reduce the timing failures, as well as to ensure the correct operations under all PVT conditions. However, increasing the clock period up to the worst-case critical path delay incurs a significant increase in the active leakage energy. This brief presents an adaptive clock generation scheme for subthreshold logics, wherein a replica module inside measures the variations and helps generate a clock with the correct period. As a result, considerable energy savings is achieved, along with a reduction in the setup time violations. The experimental results obtained with a 0.13-μm CMOS process show that the proposed scheme achieves energy savings of up to 63.8% with the selection of four different clock cycles under a supply voltage of 0.3 V.
AB - Subthreshold logic has become an attractive option in energy-constrained applications, where the key metric is energy consumption rather than operating speed or silicon area. However, the performance of circuits operating in the subthreshold region is extremely sensitive to the variations in the process, supply voltage, and temperature (PVT). Generally, circuit designers increase the clock period in order to reduce the timing failures, as well as to ensure the correct operations under all PVT conditions. However, increasing the clock period up to the worst-case critical path delay incurs a significant increase in the active leakage energy. This brief presents an adaptive clock generation scheme for subthreshold logics, wherein a replica module inside measures the variations and helps generate a clock with the correct period. As a result, considerable energy savings is achieved, along with a reduction in the setup time violations. The experimental results obtained with a 0.13-μm CMOS process show that the proposed scheme achieves energy savings of up to 63.8% with the selection of four different clock cycles under a supply voltage of 0.3 V.
KW - Active leakage energy
KW - subthreshold logics
KW - ultralow voltage
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U2 - 10.1109/TCSII.2012.2206933
DO - 10.1109/TCSII.2012.2206933
M3 - Article
VL - 59
SP - 587
EP - 591
JO - IEEE Transactions on Circuits and Systems I: Regular Papers
JF - IEEE Transactions on Circuits and Systems I: Regular Papers
SN - 1549-8328
IS - 9
M1 - 6247477
ER -