Abstract
An all-digital duty-cycle corrector with a wide duty correction range and fast correction time is hereby presented. The proposed corrector uses a 1-bit digital duty-cycle detector with a time-to-digital converter, and it achieves a duty correction range between 10% and 90% with a low pressure, volume, and temperature variation. The test chip was fabricated using a 0.13-μm CMOS process, and it occupies an area of 0.059 mm2. The correction cycle is a 14 cycles and the duty-cycle error is below ±1.4%. At an operating frequency of 1 GHz, the power dissipation and peak-to-peak jitter are measured at 5.6 mW and 20.5 ps, respectively.
| Original language | English |
|---|---|
| Article number | 7041224 |
| Pages (from-to) | 363-367 |
| Number of pages | 5 |
| Journal | IEEE Transactions on Very Large Scale Integration (VLSI) Systems |
| Volume | 24 |
| Issue number | 1 |
| DOIs | |
| Publication status | Published - 2016 Jan 1 |
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Keywords
- Digital comparator
- double data rate
- DRAM
- duty-cycle corrector (DCC)
- successive approximation register (SAR) controller
ASJC Scopus subject areas
- Electrical and Electronic Engineering
- Hardware and Architecture
- Software
Cite this
All-Digital Duty-Cycle Corrector with a Wide Duty Correction Range for DRAM Applications. / Jeong, Chan Hui; Abdullah, Ammar; Min, Young Jae; Hwang, In Chul; Kim, Soo-Won.
In: IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 24, No. 1, 7041224, 01.01.2016, p. 363-367.Research output: Contribution to journal › Article
}
TY - JOUR
T1 - All-Digital Duty-Cycle Corrector with a Wide Duty Correction Range for DRAM Applications
AU - Jeong, Chan Hui
AU - Abdullah, Ammar
AU - Min, Young Jae
AU - Hwang, In Chul
AU - Kim, Soo-Won
PY - 2016/1/1
Y1 - 2016/1/1
N2 - An all-digital duty-cycle corrector with a wide duty correction range and fast correction time is hereby presented. The proposed corrector uses a 1-bit digital duty-cycle detector with a time-to-digital converter, and it achieves a duty correction range between 10% and 90% with a low pressure, volume, and temperature variation. The test chip was fabricated using a 0.13-μm CMOS process, and it occupies an area of 0.059 mm2. The correction cycle is a 14 cycles and the duty-cycle error is below ±1.4%. At an operating frequency of 1 GHz, the power dissipation and peak-to-peak jitter are measured at 5.6 mW and 20.5 ps, respectively.
AB - An all-digital duty-cycle corrector with a wide duty correction range and fast correction time is hereby presented. The proposed corrector uses a 1-bit digital duty-cycle detector with a time-to-digital converter, and it achieves a duty correction range between 10% and 90% with a low pressure, volume, and temperature variation. The test chip was fabricated using a 0.13-μm CMOS process, and it occupies an area of 0.059 mm2. The correction cycle is a 14 cycles and the duty-cycle error is below ±1.4%. At an operating frequency of 1 GHz, the power dissipation and peak-to-peak jitter are measured at 5.6 mW and 20.5 ps, respectively.
KW - Digital comparator
KW - double data rate
KW - DRAM
KW - duty-cycle corrector (DCC)
KW - successive approximation register (SAR) controller
UR - http://www.scopus.com/inward/record.url?scp=84923096335&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=84923096335&partnerID=8YFLogxK
U2 - 10.1109/TVLSI.2015.2394486
DO - 10.1109/TVLSI.2015.2394486
M3 - Article
AN - SCOPUS:84923096335
VL - 24
SP - 363
EP - 367
JO - IEEE Transactions on Very Large Scale Integration (VLSI) Systems
JF - IEEE Transactions on Very Large Scale Integration (VLSI) Systems
SN - 1063-8210
IS - 1
M1 - 7041224
ER -