All-Digital Duty-Cycle Corrector with a Wide Duty Correction Range for DRAM Applications

Chan Hui Jeong, Ammar Abdullah, Young Jae Min, In Chul Hwang, Soo-Won Kim

Research output: Contribution to journalArticle

12 Citations (Scopus)

Abstract

An all-digital duty-cycle corrector with a wide duty correction range and fast correction time is hereby presented. The proposed corrector uses a 1-bit digital duty-cycle detector with a time-to-digital converter, and it achieves a duty correction range between 10% and 90% with a low pressure, volume, and temperature variation. The test chip was fabricated using a 0.13-μm CMOS process, and it occupies an area of 0.059 mm2. The correction cycle is a 14 cycles and the duty-cycle error is below ±1.4%. At an operating frequency of 1 GHz, the power dissipation and peak-to-peak jitter are measured at 5.6 mW and 20.5 ps, respectively.

Original languageEnglish
Article number7041224
Pages (from-to)363-367
Number of pages5
JournalIEEE Transactions on Very Large Scale Integration (VLSI) Systems
Volume24
Issue number1
DOIs
Publication statusPublished - 2016 Jan 1

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Keywords

  • Digital comparator
  • double data rate
  • DRAM
  • duty-cycle corrector (DCC)
  • successive approximation register (SAR) controller

ASJC Scopus subject areas

  • Electrical and Electronic Engineering
  • Hardware and Architecture
  • Software

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