An 11-b 100-MS/s Fully Dynamic Pipelined ADC Using a High-Linearity Dynamic Amplifier

Yunsoo Park, Jaegeun Song, Yohan Choi, Chaegang Lim, Soonsung Ahn, Chulwoo Kim

Research output: Contribution to journalArticlepeer-review

3 Citations (Scopus)

Abstract

This article reports a high-linearity dynamic amplifier with a gain control technique for pipelined analog-to-digital converters (ADCs). The wide input range and dynamic operation of the amplifier allow the ADC energy-efficient pipeline process. The voltage gain is controlled in the analog domain with digital gain correction codes, enabling simple compensation for process, voltage, and temperature variations. The proposed switching technique for the amplifier also defines a stable common-mode output without any dedicated hardware. An 11-bit 100-MS/s fully dynamic pipelined ADC using the open-loop dynamic amplifier is implemented without gain-linearity calibration. An ADC prototype is fabricated in a 28-nm CMOS process with an active area of 0.05 mm2, and the performances are measured at sampling rates in the range of 10-100 MHz. This ADC achieves a signal-to-noise and distortion ratio of 62 dB and a spurious-free dynamic range of 77 dB while consuming 1.33 mW of power at 100 MS/s. A Walden figure of merit of 10.8-13.1 fJ/conversion-step is achieved.

Original languageEnglish
Article number9079902
Pages (from-to)2468-2477
Number of pages10
JournalIEEE Journal of Solid-State Circuits
Volume55
Issue number9
DOIs
Publication statusPublished - 2020 Sep

Keywords

  • Analog-to-digital conversion
  • dynamic residue amplifier
  • fully dynamic pipelined analog-to-digital converter (ADC)
  • integrator
  • linearity
  • open-loop amplifier

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

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