An 80-dB SNR 4th-order discrete-time sigma-delta modulator

Chan Keun Kwon, Chan Hui Jeong, Young Jae Min, Young Mok Jung, Soo Won Kim

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Citation (Scopus)

Abstract

This paper presents a 4th-order single-bit DT ΔΣ modulator for audio applications. To achieve higher signal-to-noise ratio (SNR), the compensation capacitors in the input of a comparator are exploited to reduce the metastability of a comparator. The proposed modulator has been fabricated in a quantizer level 0.18-μm CMOS process. Measurements show a SNR of 80.27 dB and a signal-to-noise and distortion ratio (SNDR) of 77.58 dB over a 40-kHz signal bandwidth with a sampling clock frequency of 10.24 MHz. A total power consumption including a clock generator is 340 μW with a 1.8-V supply voltage.

Original languageEnglish
Title of host publication2011 International Symposium on Integrated Circuits, ISIC 2011
Pages230-233
Number of pages4
DOIs
Publication statusPublished - 2011
Event2011 International Symposium on Integrated Circuits, ISIC 2011 - SingaporeSingapore, Singapore
Duration: 2011 Dec 122011 Dec 14

Publication series

Name2011 International Symposium on Integrated Circuits, ISIC 2011

Other

Other2011 International Symposium on Integrated Circuits, ISIC 2011
CountrySingapore
CitySingaporeSingapore
Period11/12/1211/12/14

Keywords

  • Analog-to-digital converter
  • Comparator-metastability
  • Compensation capacitor
  • Discrete-time ΔΣ modulator

ASJC Scopus subject areas

  • Hardware and Architecture
  • Electrical and Electronic Engineering

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  • Cite this

    Kwon, C. K., Jeong, C. H., Min, Y. J., Jung, Y. M., & Kim, S. W. (2011). An 80-dB SNR 4th-order discrete-time sigma-delta modulator. In 2011 International Symposium on Integrated Circuits, ISIC 2011 (pp. 230-233). [6131938] (2011 International Symposium on Integrated Circuits, ISIC 2011). https://doi.org/10.1109/ISICir.2011.6131938