An 80nm 4Gb/s/pin 32b 512Mb GDDR4 graphics DRAM with low-power and low-noise data-bus inversion

Jeong Don Ihm, Seung Jun Bae, Kwang Il Park, Ho Young Song, Woo Jin Lee, Hyun Jin Kim, Kyung Ho Kim, Ho Kyung Lee, Min Sang Park, Sam Young Bang, Mi Jin Lee, Gil Shin Moon, Young Wook Jang, Suk Won Hwang, Young Chul Cho, Sang Jun Hwang, Dae Hyun Kim, Ji Hoon Lim, Jae Sung Kim, Su Jin ParkOk Joo Park, Se Mi Yang, Jin Yong Choi, Young Wook Kim, Hyun Kyu Lee, Sung Hoon Kim, Seong Jin Jang, Young Hyun Jun, Soo In Cho

Research output: Chapter in Book/Report/Conference proceedingConference contribution

15 Citations (Scopus)

Abstract

A 4Gb/s/pin 32b parallel 512Mb GDDR4 SDRAM is implemented in an 80nm DRAM process. It employs a data-bus inversion coding scheme with an analog majority voter insensitive to mismatch, which reduces peak-to-peak jitter by 21ps and voltage fluctuation by 68mV. A dual duty-cycle corrector is proposed to average duty error, and tuning is added to the auto-calibration of driver and termination impedance.

Original languageEnglish
Title of host publication2007 IEEE International Solid-State Circuits Conference, ISSCC - Digest of Technical Papers
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages492-494
Number of pages3
ISBN (Print)1424408539, 9781424408535
DOIs
Publication statusPublished - 2007
Externally publishedYes
Event54th IEEE International Solid-State Circuits Conference, ISSCC 2007 - San Francisco, CA, United States
Duration: 2007 Feb 112007 Feb 15

Publication series

NameDigest of Technical Papers - IEEE International Solid-State Circuits Conference
ISSN (Print)0193-6530

Other

Other54th IEEE International Solid-State Circuits Conference, ISSCC 2007
CountryUnited States
CitySan Francisco, CA
Period07/2/1107/2/15

ASJC Scopus subject areas

  • Electronic, Optical and Magnetic Materials
  • Electrical and Electronic Engineering

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