An adaptive-bandwidth PLL for avoiding noise interference and DFE-less fast precharge sampling for over 10Gb/s/pin graphics DRAM interface

Junyoung Song, Hyun Woo Lee, Soo Bin Lim, Sewook Hwang, Yunsaing Kim, Young Jung Choi, Byong Tae Chung, Chulwoo Kim

Research output: Chapter in Book/Report/Conference proceedingConference contribution

4 Citations (Scopus)

Abstract

DRAM speed already reaches 7Gb/s/pin for GDDR interface [1,4]. As the bit rate increases, jitter of PLL, data-sampling margin, crosstalk and intersymbol interference (ISI) needs considerable management [1,3,5]. Moreover, as the supply voltage decreases, the self-generated internal noise of DRAM increases due to low efficiency of the internal voltage generator, especially the VPP voltage generator [2]. In general, the sensitivity of PLL to supply noise gives rise to large jitter accumulation. If the supply noise frequency is close to the PLL bandwidth, more jitter peaking occurs. Therefore, the PLL bandwidth is an important parameter to achieve low jitter performance [3]. Crosstalk becomes a crucial issue for over 7Gb/s GDDR interface [1]. However, the complexity of the transmitter and the CIO, capacitance of I/O, increase due to additional equalizers and pre- and de-emphasis drivers. For a compact transmitter, a low-overhead boosted transmitter is developed [4]. This paper presents an adaptive-bandwidth PLL in response to the supply and channel noises, a fast pre-charged data sampler without an additional decision-feedback equalizer (DFE), a crosstalk-induced-jitter-reduction technique and a compact transmitter with pre- and de-emphasis.

Original languageEnglish
Title of host publication2013 IEEE International Solid-State Circuits Conference, ISSCC 2013 - Digest of Technical Papers
Pages312-313
Number of pages2
DOIs
Publication statusPublished - 2013
Event2013 60th IEEE International Solid-State Circuits Conference, ISSCC 2013 - San Francisco, CA, United States
Duration: 2013 Feb 172013 Feb 21

Publication series

NameDigest of Technical Papers - IEEE International Solid-State Circuits Conference
Volume56
ISSN (Print)0193-6530

Other

Other2013 60th IEEE International Solid-State Circuits Conference, ISSCC 2013
CountryUnited States
CitySan Francisco, CA
Period13/2/1713/2/21

ASJC Scopus subject areas

  • Electronic, Optical and Magnetic Materials
  • Electrical and Electronic Engineering

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    Song, J., Lee, H. W., Lim, S. B., Hwang, S., Kim, Y., Choi, Y. J., Chung, B. T., & Kim, C. (2013). An adaptive-bandwidth PLL for avoiding noise interference and DFE-less fast precharge sampling for over 10Gb/s/pin graphics DRAM interface. In 2013 IEEE International Solid-State Circuits Conference, ISSCC 2013 - Digest of Technical Papers (pp. 312-313). [6487749] (Digest of Technical Papers - IEEE International Solid-State Circuits Conference; Vol. 56). https://doi.org/10.1109/ISSCC.2013.6487749