An add-on type real-time jitter tolerance enhancer for digital communication receivers

Sewook Hwang, Junyoung Song, Sang Geun Bae, Yeonho Lee, Chulwoo Kim

Research output: Contribution to journalArticlepeer-review

1 Citation (Scopus)

Abstract

An add-on type real-time jitter tolerance enhancer (JTE) is presented in this paper. The proposed JTE can improve high-frequency jitter tolerance (JTOL) by using a real-time phase alignment scheme. A mathematical analysis for an advanced bit error rate (BER) prediction method is also introduced. The proposed circuit is applicable to various types of receivers, such as referenceless receivers, receivers with a reference clock source, and source-synchronous receivers. The referenceless receiver with the proposed JTE achieved an out-ofband JTOL of 0.71 UIpp at 100 MHz with <10-12 BER. This is 196% higher than a conventional receiver without the JTE. The source-synchronous receiver with the proposed JTE achieved 0.92 UIpp at 300 MHz with <10-12 BER. Total core areas of the receiver and JTE are 0.19 and 0.07 mm2 in a 0.13-μm CMOS process, respectively. The power consumption of the receiver is 38 mW at 5.4 Gbit/s, and the JTE dissipates 22 mW.

Original languageEnglish
Article number2435026
Pages (from-to)1092-1103
Number of pages12
JournalIEEE Transactions on Very Large Scale Integration (VLSI) Systems
Volume24
Issue number3
DOIs
Publication statusPublished - 2016 Mar

Keywords

  • Bit error rate (BER)
  • Jitter tolerance (JTOL)
  • Real-time jitter tolerance enhancer (JTE)
  • Receiver (Rx)

ASJC Scopus subject areas

  • Software
  • Hardware and Architecture
  • Electrical and Electronic Engineering

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