An add-on type real-time jitter tolerance enhancer for digital communication receivers

Sewook Hwang; Junyoung Song; Sang Geun Bae; Yeonho Lee; Chulwoo Kim

doi:10.1109/TVLSI.2015.2435026

An add-on type real-time jitter tolerance enhancer for digital communication receivers

Sewook Hwang, Junyoung Song, Sang Geun Bae, Yeonho Lee, Chulwoo Kim

School of Electrical Engineering

Research output: Contribution to journal › Article

1 Citation (Scopus)

Abstract

An add-on type real-time jitter tolerance enhancer (JTE) is presented in this paper. The proposed JTE can improve high-frequency jitter tolerance (JTOL) by using a real-time phase alignment scheme. A mathematical analysis for an advanced bit error rate (BER) prediction method is also introduced. The proposed circuit is applicable to various types of receivers, such as referenceless receivers, receivers with a reference clock source, and source-synchronous receivers. The referenceless receiver with the proposed JTE achieved an out-ofband JTOL of 0.71 UIpp at 100 MHz with

Original language	English
Article number	2435026
Pages (from-to)	1092-1103
Number of pages	12
Journal	IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Volume	24
Issue number	3
DOIs	https://doi.org/10.1109/TVLSI.2015.2435026
Publication status	Published - 2016 Mar 1

Keywords

Bit error rate (BER)
Jitter tolerance (JTOL)
Real-time jitter tolerance enhancer (JTE)
Receiver (Rx)

ASJC Scopus subject areas

Electrical and Electronic Engineering
Hardware and Architecture
Software

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Hwang, S., Song, J., Bae, S. G., Lee, Y., & Kim, C. (2016). An add-on type real-time jitter tolerance enhancer for digital communication receivers. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 24(3), 1092-1103. [2435026]. https://doi.org/10.1109/TVLSI.2015.2435026

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