An add-on type real-time jitter tolerance enhancer for digital communication receivers

Sewook Hwang, Junyoung Song, Sang Geun Bae, Yeonho Lee, Chulwoo Kim

Research output: Contribution to journalArticle

1 Citation (Scopus)

Abstract

An add-on type real-time jitter tolerance enhancer (JTE) is presented in this paper. The proposed JTE can improve high-frequency jitter tolerance (JTOL) by using a real-time phase alignment scheme. A mathematical analysis for an advanced bit error rate (BER) prediction method is also introduced. The proposed circuit is applicable to various types of receivers, such as referenceless receivers, receivers with a reference clock source, and source-synchronous receivers. The referenceless receiver with the proposed JTE achieved an out-ofband JTOL of 0.71 UIpp at 100 MHz with

Original languageEnglish
Article number2435026
Pages (from-to)1092-1103
Number of pages12
JournalIEEE Transactions on Very Large Scale Integration (VLSI) Systems
Volume24
Issue number3
DOIs
Publication statusPublished - 2016 Mar 1

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Jitter
Communication
Bit error rate
Clocks
Networks (circuits)

Keywords

  • Bit error rate (BER)
  • Jitter tolerance (JTOL)
  • Real-time jitter tolerance enhancer (JTE)
  • Receiver (Rx)

ASJC Scopus subject areas

  • Electrical and Electronic Engineering
  • Hardware and Architecture
  • Software

Cite this

An add-on type real-time jitter tolerance enhancer for digital communication receivers. / Hwang, Sewook; Song, Junyoung; Bae, Sang Geun; Lee, Yeonho; Kim, Chulwoo.

In: IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 24, No. 3, 2435026, 01.03.2016, p. 1092-1103.

Research output: Contribution to journalArticle

Hwang, Sewook ; Song, Junyoung ; Bae, Sang Geun ; Lee, Yeonho ; Kim, Chulwoo. / An add-on type real-time jitter tolerance enhancer for digital communication receivers. In: IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 2016 ; Vol. 24, No. 3. pp. 1092-1103.
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