TY - JOUR
T1 - An add-on type real-time jitter tolerance enhancer for digital communication receivers
AU - Hwang, Sewook
AU - Song, Junyoung
AU - Bae, Sang Geun
AU - Lee, Yeonho
AU - Kim, Chulwoo
N1 - Funding Information:
This work was supported by the National Research Foundation of Korea through the Korea Government within the Ministry of Education, Science and Technology under Grant NRF-2011-0020128. Fabrication was supported by the MPW of IDEC.
PY - 2016/3
Y1 - 2016/3
N2 - An add-on type real-time jitter tolerance enhancer (JTE) is presented in this paper. The proposed JTE can improve high-frequency jitter tolerance (JTOL) by using a real-time phase alignment scheme. A mathematical analysis for an advanced bit error rate (BER) prediction method is also introduced. The proposed circuit is applicable to various types of receivers, such as referenceless receivers, receivers with a reference clock source, and source-synchronous receivers. The referenceless receiver with the proposed JTE achieved an out-ofband JTOL of 0.71 UIpp at 100 MHz with <10-12 BER. This is 196% higher than a conventional receiver without the JTE. The source-synchronous receiver with the proposed JTE achieved 0.92 UIpp at 300 MHz with <10-12 BER. Total core areas of the receiver and JTE are 0.19 and 0.07 mm2 in a 0.13-μm CMOS process, respectively. The power consumption of the receiver is 38 mW at 5.4 Gbit/s, and the JTE dissipates 22 mW.
AB - An add-on type real-time jitter tolerance enhancer (JTE) is presented in this paper. The proposed JTE can improve high-frequency jitter tolerance (JTOL) by using a real-time phase alignment scheme. A mathematical analysis for an advanced bit error rate (BER) prediction method is also introduced. The proposed circuit is applicable to various types of receivers, such as referenceless receivers, receivers with a reference clock source, and source-synchronous receivers. The referenceless receiver with the proposed JTE achieved an out-ofband JTOL of 0.71 UIpp at 100 MHz with <10-12 BER. This is 196% higher than a conventional receiver without the JTE. The source-synchronous receiver with the proposed JTE achieved 0.92 UIpp at 300 MHz with <10-12 BER. Total core areas of the receiver and JTE are 0.19 and 0.07 mm2 in a 0.13-μm CMOS process, respectively. The power consumption of the receiver is 38 mW at 5.4 Gbit/s, and the JTE dissipates 22 mW.
KW - Bit error rate (BER)
KW - Jitter tolerance (JTOL)
KW - Real-time jitter tolerance enhancer (JTE)
KW - Receiver (Rx)
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U2 - 10.1109/TVLSI.2015.2435026
DO - 10.1109/TVLSI.2015.2435026
M3 - Article
AN - SCOPUS:84931086233
VL - 24
SP - 1092
EP - 1103
JO - IEEE Transactions on Very Large Scale Integration (VLSI) Systems
JF - IEEE Transactions on Very Large Scale Integration (VLSI) Systems
SN - 1063-8210
IS - 3
M1 - 2435026
ER -