An advanced bit-line clamping scheme in magnetic RAM for wide sensing margin

Jong Chul Lim, Hye Seung Yu, Jae Suk Choi, Soo-Won Kim

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

This paper proposes the bit-line clamping scheme for a stable signal margin in Magnetoresistance RAM. MRAM distinguishes data by the difference of resistance in MTJ. However, there are so many error sources in MTJ that it limits a yield factor. In this paper, we focus on the resistance variation due to bit-line voltage. For maximum signal difference, we try to reduce bit-line voltage as low as possible. Proposed scheme employs CBLSA, equalizer transistor and ITIMTJ array structure. This method has very excellent bit-line clamping characteristic and overall memory can be designed a simple architecture using current mode sensing. As a result, proposed memory structure can clamp a bit-line voltage under 0.15V and it uses very small power and area. This lower bit-line voltage promises more stable data accessing in MRAM. The circuit is designed in a 0.35um-CMOS technology.

Original languageEnglish
Title of host publicationProceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC
Pages877-882
Number of pages6
Volume2
Publication statusPublished - 2005 Dec 1
Event2005 Asia and South Pacific Design Automation Conference, ASP-DAC 2005 - Shanghai, China
Duration: 2005 Jan 182005 Jan 21

Other

Other2005 Asia and South Pacific Design Automation Conference, ASP-DAC 2005
CountryChina
CityShanghai
Period05/1/1805/1/21

Fingerprint

Random access storage
Electric potential
Data storage equipment
Clamping devices
Magnetoresistance
Equalizers
Transistors
Networks (circuits)

ASJC Scopus subject areas

  • Electrical and Electronic Engineering
  • Computer Science Applications
  • Computer Graphics and Computer-Aided Design

Cite this

Lim, J. C., Yu, H. S., Choi, J. S., & Kim, S-W. (2005). An advanced bit-line clamping scheme in magnetic RAM for wide sensing margin. In Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC (Vol. 2, pp. 877-882). [1466480]

An advanced bit-line clamping scheme in magnetic RAM for wide sensing margin. / Lim, Jong Chul; Yu, Hye Seung; Choi, Jae Suk; Kim, Soo-Won.

Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC. Vol. 2 2005. p. 877-882 1466480.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Lim, JC, Yu, HS, Choi, JS & Kim, S-W 2005, An advanced bit-line clamping scheme in magnetic RAM for wide sensing margin. in Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC. vol. 2, 1466480, pp. 877-882, 2005 Asia and South Pacific Design Automation Conference, ASP-DAC 2005, Shanghai, China, 05/1/18.
Lim JC, Yu HS, Choi JS, Kim S-W. An advanced bit-line clamping scheme in magnetic RAM for wide sensing margin. In Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC. Vol. 2. 2005. p. 877-882. 1466480
Lim, Jong Chul ; Yu, Hye Seung ; Choi, Jae Suk ; Kim, Soo-Won. / An advanced bit-line clamping scheme in magnetic RAM for wide sensing margin. Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC. Vol. 2 2005. pp. 877-882
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