An all digital time amplifier with interpolation scheme for low gain variation

Debashis Dhar, Young Ho Kwak, Inhwa Jung, Chulwoo Kim

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

An all digital time amplifier (TA) is proposed in 0.13 μm CMOS process. The TA is based on quantization scheme; hence it guarantees large input range. An interpolation scheme is employed to achieve more than 2 times reduction in gain variation of the TA over the input range. The all digital TA is portable to other process technology with smaller design effort. The TA shows a gain variation of less than 5% and consumes a power of 14 mW.

Original languageEnglish
Title of host publication2010 International SoC Design Conference, ISOCC 2010
Pages276-278
Number of pages3
DOIs
Publication statusPublished - 2010 Dec 1
Event2010 International SoC Design Conference, ISOCC 2010 - Incheon, Korea, Republic of
Duration: 2010 Nov 222010 Nov 23

Other

Other2010 International SoC Design Conference, ISOCC 2010
CountryKorea, Republic of
CityIncheon
Period10/11/2210/11/23

Fingerprint

Interpolation

Keywords

  • All digital time amplifier
  • Interpolation

ASJC Scopus subject areas

  • Hardware and Architecture

Cite this

Dhar, D., Kwak, Y. H., Jung, I., & Kim, C. (2010). An all digital time amplifier with interpolation scheme for low gain variation. In 2010 International SoC Design Conference, ISOCC 2010 (pp. 276-278). [5682917] https://doi.org/10.1109/SOCDC.2010.5682917

An all digital time amplifier with interpolation scheme for low gain variation. / Dhar, Debashis; Kwak, Young Ho; Jung, Inhwa; Kim, Chulwoo.

2010 International SoC Design Conference, ISOCC 2010. 2010. p. 276-278 5682917.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Dhar, D, Kwak, YH, Jung, I & Kim, C 2010, An all digital time amplifier with interpolation scheme for low gain variation. in 2010 International SoC Design Conference, ISOCC 2010., 5682917, pp. 276-278, 2010 International SoC Design Conference, ISOCC 2010, Incheon, Korea, Republic of, 10/11/22. https://doi.org/10.1109/SOCDC.2010.5682917
Dhar D, Kwak YH, Jung I, Kim C. An all digital time amplifier with interpolation scheme for low gain variation. In 2010 International SoC Design Conference, ISOCC 2010. 2010. p. 276-278. 5682917 https://doi.org/10.1109/SOCDC.2010.5682917
Dhar, Debashis ; Kwak, Young Ho ; Jung, Inhwa ; Kim, Chulwoo. / An all digital time amplifier with interpolation scheme for low gain variation. 2010 International SoC Design Conference, ISOCC 2010. 2010. pp. 276-278
@inproceedings{997f7f7aadf34cf18e1b7cf3ac9b0988,
title = "An all digital time amplifier with interpolation scheme for low gain variation",
abstract = "An all digital time amplifier (TA) is proposed in 0.13 μm CMOS process. The TA is based on quantization scheme; hence it guarantees large input range. An interpolation scheme is employed to achieve more than 2 times reduction in gain variation of the TA over the input range. The all digital TA is portable to other process technology with smaller design effort. The TA shows a gain variation of less than 5{\%} and consumes a power of 14 mW.",
keywords = "All digital time amplifier, Interpolation",
author = "Debashis Dhar and Kwak, {Young Ho} and Inhwa Jung and Chulwoo Kim",
year = "2010",
month = "12",
day = "1",
doi = "10.1109/SOCDC.2010.5682917",
language = "English",
isbn = "9781424486335",
pages = "276--278",
booktitle = "2010 International SoC Design Conference, ISOCC 2010",

}

TY - GEN

T1 - An all digital time amplifier with interpolation scheme for low gain variation

AU - Dhar, Debashis

AU - Kwak, Young Ho

AU - Jung, Inhwa

AU - Kim, Chulwoo

PY - 2010/12/1

Y1 - 2010/12/1

N2 - An all digital time amplifier (TA) is proposed in 0.13 μm CMOS process. The TA is based on quantization scheme; hence it guarantees large input range. An interpolation scheme is employed to achieve more than 2 times reduction in gain variation of the TA over the input range. The all digital TA is portable to other process technology with smaller design effort. The TA shows a gain variation of less than 5% and consumes a power of 14 mW.

AB - An all digital time amplifier (TA) is proposed in 0.13 μm CMOS process. The TA is based on quantization scheme; hence it guarantees large input range. An interpolation scheme is employed to achieve more than 2 times reduction in gain variation of the TA over the input range. The all digital TA is portable to other process technology with smaller design effort. The TA shows a gain variation of less than 5% and consumes a power of 14 mW.

KW - All digital time amplifier

KW - Interpolation

UR - http://www.scopus.com/inward/record.url?scp=79851471660&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=79851471660&partnerID=8YFLogxK

U2 - 10.1109/SOCDC.2010.5682917

DO - 10.1109/SOCDC.2010.5682917

M3 - Conference contribution

AN - SCOPUS:79851471660

SN - 9781424486335

SP - 276

EP - 278

BT - 2010 International SoC Design Conference, ISOCC 2010

ER -