An all digital time amplifier with interpolation scheme for low gain variation

Debashis Dhar, Young Ho Kwak, Inhwa Jung, Chulwoo Kim

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Citation (Scopus)

Abstract

An all digital time amplifier (TA) is proposed in 0.13 μm CMOS process. The TA is based on quantization scheme; hence it guarantees large input range. An interpolation scheme is employed to achieve more than 2 times reduction in gain variation of the TA over the input range. The all digital TA is portable to other process technology with smaller design effort. The TA shows a gain variation of less than 5% and consumes a power of 14 mW.

Original languageEnglish
Title of host publication2010 International SoC Design Conference, ISOCC 2010
Pages276-278
Number of pages3
DOIs
Publication statusPublished - 2010 Dec 1
Event2010 International SoC Design Conference, ISOCC 2010 - Incheon, Korea, Republic of
Duration: 2010 Nov 222010 Nov 23

Publication series

Name2010 International SoC Design Conference, ISOCC 2010

Other

Other2010 International SoC Design Conference, ISOCC 2010
CountryKorea, Republic of
CityIncheon
Period10/11/2210/11/23

    Fingerprint

Keywords

  • All digital time amplifier
  • Interpolation

ASJC Scopus subject areas

  • Hardware and Architecture

Cite this

Dhar, D., Kwak, Y. H., Jung, I., & Kim, C. (2010). An all digital time amplifier with interpolation scheme for low gain variation. In 2010 International SoC Design Conference, ISOCC 2010 (pp. 276-278). [5682917] (2010 International SoC Design Conference, ISOCC 2010). https://doi.org/10.1109/SOCDC.2010.5682917