This paper describes a new delay-locked loop (DLL) based frequency multiplier which includes a lock controller and a PD to prevent false locking and increase locking range relative to conventional DLLs. By using multiple clock phase of the DLL, the lock controller detects whether the VCDL delay is within a correct locking range or not. A differentially controlled edge combiner for frequency multiplication is also proposed. The anti-harmonic DLL-based frequency multiplier implemented in a 0.18 μm CMOS technology occupies an active area of 0.043 mm2 and dissipates 36.7 mW at 1.7GHz output clock. The measured RMS and peak-to-peak jitters for the multiplied output clock at 1.7GHz are 2.64ps and 16.8ps, respectively.