An anti-harmonic, programmable DLL-based frequency multiplier for dynamic frequency scaling

Kyunghoon Chung, Jabeom Koo, Soo Won Kim, Chulwoo Kim

Research output: Chapter in Book/Report/Conference proceedingConference contribution

12 Citations (Scopus)

Abstract

This paper describes a new delay-locked loop (DLL) based frequency multiplier which includes a lock controller and a PD to prevent false locking and increase locking range relative to conventional DLLs. By using multiple clock phase of the DLL, the lock controller detects whether the VCDL delay is within a correct locking range or not. A differentially controlled edge combiner for frequency multiplication is also proposed. The anti-harmonic DLL-based frequency multiplier implemented in a 0.18 μm CMOS technology occupies an active area of 0.043 mm2 and dissipates 36.7 mW at 1.7GHz output clock. The measured RMS and peak-to-peak jitters for the multiplied output clock at 1.7GHz are 2.64ps and 16.8ps, respectively.

Original languageEnglish
Title of host publication2007 IEEE Asian Solid-State Circuits Conference, A-SSCC
Pages276-279
Number of pages4
DOIs
Publication statusPublished - 2007
Event2007 IEEE Asian Solid-State Circuits Conference, A-SSCC - Jeju, Korea, Republic of
Duration: 2007 Nov 122007 Nov 14

Publication series

Name2007 IEEE Asian Solid-State Circuits Conference, A-SSCC

Other

Other2007 IEEE Asian Solid-State Circuits Conference, A-SSCC
CountryKorea, Republic of
CityJeju
Period07/11/1207/11/14

Keywords

  • DLL
  • Frequency multiplication and anti-harmonic

ASJC Scopus subject areas

  • Hardware and Architecture
  • Electrical and Electronic Engineering

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    Chung, K., Koo, J., Kim, S. W., & Kim, C. (2007). An anti-harmonic, programmable DLL-based frequency multiplier for dynamic frequency scaling. In 2007 IEEE Asian Solid-State Circuits Conference, A-SSCC (pp. 276-279). [4425684] (2007 IEEE Asian Solid-State Circuits Conference, A-SSCC). https://doi.org/10.1109/ASSCC.2007.4425684