TY - JOUR
T1 - An antiharmonic, programmable, DLL-based frequency multiplier for dynamic frequency scaling
AU - Ok, Sunghwa
AU - Chung, Kyunghoon
AU - Koo, Jabeom
AU - Kim, Chulwoo
N1 - Funding Information:
Manuscript received July 19, 2008; revised January 15, 2009; accepted March 02, 2009. First published October 09, 2009; current version published June 25, 2010. This work was supported by the National Research Foundation of Korea (NRF) under a grant funded by the Korean Government (MEST) (R0A-2007-000-20059-0), and chip fabrication was supported by the IC Design Education Center.
PY - 2010/7
Y1 - 2010/7
N2 - This paper describes a new delay-locked loop (DLL)-based frequency multiplier, which includes a lock controller and a phase detector to solve the false lock problem and overcome the limited locking range of conventional DLLs. By using the multiple clock phases of the DLL, the lock controller is able to indicate whether the delay time of the VCDL is within the correct locking range or not. A differentially controlled edge combiner is also proposed for the frequency multiplication. The antiharmonic DLL-based frequency multiplier, implemented in a 0.18-μm CMOS process, occupies an active area of 0.043 mm2, and dissipates 36.7 mW at 1.7 GHz. The measured root mean square jitter and peak-to-peak jitter for the multiplied output clock at 1.7 GHz are 2.64 and 16.8 ps, respectively.
AB - This paper describes a new delay-locked loop (DLL)-based frequency multiplier, which includes a lock controller and a phase detector to solve the false lock problem and overcome the limited locking range of conventional DLLs. By using the multiple clock phases of the DLL, the lock controller is able to indicate whether the delay time of the VCDL is within the correct locking range or not. A differentially controlled edge combiner is also proposed for the frequency multiplication. The antiharmonic DLL-based frequency multiplier, implemented in a 0.18-μm CMOS process, occupies an active area of 0.043 mm2, and dissipates 36.7 mW at 1.7 GHz. The measured root mean square jitter and peak-to-peak jitter for the multiplied output clock at 1.7 GHz are 2.64 and 16.8 ps, respectively.
KW - Antiharmonic lock
KW - delay-locked loop (DLL)
KW - false lock
KW - frequency multiplication
KW - limited locking range
UR - http://www.scopus.com/inward/record.url?scp=77954083773&partnerID=8YFLogxK
U2 - 10.1109/TVLSI.2009.2019757
DO - 10.1109/TVLSI.2009.2019757
M3 - Article
AN - SCOPUS:77954083773
SN - 1063-8210
VL - 18
SP - 1130
EP - 1134
JO - IEEE Transactions on Very Large Scale Integration (VLSI) Systems
JF - IEEE Transactions on Very Large Scale Integration (VLSI) Systems
IS - 7
M1 - 5282518
ER -