An efficient architecture of encoder and decoder for displayport physical layer

Yongtae Kim; Junyoung Song; Woonhyung Heo; Chulwoo Kim

doi:10.1109/ICCE.2009.5012215

An efficient architecture of encoder and decoder for displayport physical layer

Yongtae Kim, Junyoung Song, Woonhyung Heo, Chulwoo Kim

School of Electrical Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

2 Citations (Scopus)

Abstract

This paper presents an efficient architecture of encoder and decoder for DisplayPort. The proposed architecture provides high-speed and low-complexity for the hardware specified by the DisplayPort standard. Moreover, the encoder and decoder require gate counts of only 0.94K and 0.89K, respectively.

Original language	English
Title of host publication	2009 Digest of Technical Papers International Conference on Consumer Electronics, ICCE 2009
DOIs	https://doi.org/10.1109/ICCE.2009.5012215
Publication status	Published - 2009
Event	2009 International Conference on Consumer Electronics, ICCE 2009 - Las Vegas, NV, United States Duration: 2009 Jan 10 → 2009 Jan 14

Publication series

Name	Digest of Technical Papers - IEEE International Conference on Consumer Electronics
ISSN (Print)	0747-668X

Other

Other	2009 International Conference on Consumer Electronics, ICCE 2009
Country/Territory	United States
City	Las Vegas, NV
Period	09/1/10 → 09/1/14

ASJC Scopus subject areas

Industrial and Manufacturing Engineering
Electrical and Electronic Engineering

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10.1109/ICCE.2009.5012215

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An efficient architecture of encoder and decoder for displayport physical layer. / Kim, Yongtae; Song, Junyoung; Heo, Woonhyung; Kim, Chulwoo.

2009 Digest of Technical Papers International Conference on Consumer Electronics, ICCE 2009. 2009. 5012215 (Digest of Technical Papers - IEEE International Conference on Consumer Electronics).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Kim, Y, Song, J, Heo, W & Kim, C 2009, An efficient architecture of encoder and decoder for displayport physical layer. in 2009 Digest of Technical Papers International Conference on Consumer Electronics, ICCE 2009., 5012215, Digest of Technical Papers - IEEE International Conference on Consumer Electronics, 2009 International Conference on Consumer Electronics, ICCE 2009, Las Vegas, NV, United States, 09/1/10. https://doi.org/10.1109/ICCE.2009.5012215

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abstract = "This paper presents an efficient architecture of encoder and decoder for DisplayPort. The proposed architecture provides high-speed and low-complexity for the hardware specified by the DisplayPort standard. Moreover, the encoder and decoder require gate counts of only 0.94K and 0.89K, respectively.",

author = "Yongtae Kim and Junyoung Song and Woonhyung Heo and Chulwoo Kim",

year = "2009",

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AB - This paper presents an efficient architecture of encoder and decoder for DisplayPort. The proposed architecture provides high-speed and low-complexity for the hardware specified by the DisplayPort standard. Moreover, the encoder and decoder require gate counts of only 0.94K and 0.89K, respectively.

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Y2 - 10 January 2009 through 14 January 2009

ER -

An efficient architecture of encoder and decoder for displayport physical layer

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