An efficient architecture of encoder and decoder for displayport physical layer

Yongtae Kim, Junyoung Song, Woonhyung Heo, Chulwoo Kim

Research output: Chapter in Book/Report/Conference proceedingConference contribution

2 Citations (Scopus)

Abstract

This paper presents an efficient architecture of encoder and decoder for DisplayPort. The proposed architecture provides high-speed and low-complexity for the hardware specified by the DisplayPort standard. Moreover, the encoder and decoder require gate counts of only 0.94K and 0.89K, respectively.

Original languageEnglish
Title of host publication2009 Digest of Technical Papers International Conference on Consumer Electronics, ICCE 2009
DOIs
Publication statusPublished - 2009
Event2009 International Conference on Consumer Electronics, ICCE 2009 - Las Vegas, NV, United States
Duration: 2009 Jan 102009 Jan 14

Publication series

NameDigest of Technical Papers - IEEE International Conference on Consumer Electronics
ISSN (Print)0747-668X

Other

Other2009 International Conference on Consumer Electronics, ICCE 2009
CountryUnited States
CityLas Vegas, NV
Period09/1/1009/1/14

ASJC Scopus subject areas

  • Industrial and Manufacturing Engineering
  • Electrical and Electronic Engineering

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  • Cite this

    Kim, Y., Song, J., Heo, W., & Kim, C. (2009). An efficient architecture of encoder and decoder for displayport physical layer. In 2009 Digest of Technical Papers International Conference on Consumer Electronics, ICCE 2009 [5012215] (Digest of Technical Papers - IEEE International Conference on Consumer Electronics). https://doi.org/10.1109/ICCE.2009.5012215