TY - GEN
T1 - An efficient architecture of encoder and decoder for displayport physical layer
AU - Kim, Yongtae
AU - Song, Junyoung
AU - Heo, Woonhyung
AU - Kim, Chulwoo
PY - 2009
Y1 - 2009
N2 - This paper presents an efficient architecture of encoder and decoder for DisplayPort. The proposed architecture provides high-speed and low-complexity for the hardware specified by the DisplayPort standard. Moreover, the encoder and decoder require gate counts of only 0.94K and 0.89K, respectively.
AB - This paper presents an efficient architecture of encoder and decoder for DisplayPort. The proposed architecture provides high-speed and low-complexity for the hardware specified by the DisplayPort standard. Moreover, the encoder and decoder require gate counts of only 0.94K and 0.89K, respectively.
UR - http://www.scopus.com/inward/record.url?scp=70349281891&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=70349281891&partnerID=8YFLogxK
U2 - 10.1109/ICCE.2009.5012215
DO - 10.1109/ICCE.2009.5012215
M3 - Conference contribution
AN - SCOPUS:70349281891
SN - 9781424425594
T3 - Digest of Technical Papers - IEEE International Conference on Consumer Electronics
BT - 2009 Digest of Technical Papers International Conference on Consumer Electronics, ICCE 2009
T2 - 2009 International Conference on Consumer Electronics, ICCE 2009
Y2 - 10 January 2009 through 14 January 2009
ER -