An efficient convolutional neural networks design with heterogeneous SRAM cell sizing

Wonseok Choi, Jongsun Park

Research output: Chapter in Book/Report/Conference proceedingConference contribution

2 Citations (Scopus)


Deep neural networks (DNNs) have been recently achieving state-of-the-art performance for many artificial intelligence (AI) applications such as computer vision, image recognition, and machine translator. Among them, image recognition using convolutional neural networks (CNNs) is widely used, but the implementation of CNN accelerator for mobile devices is largely restricted due to its intensive computation complexity and a large amount of memory access. In this paper, we adopt the heterogeneous SRAM sizing approach for the memories in CNN processor, where more important higher order data bits are stored in the relatively larger SRAM bit-cells and the less important bits are stored in the smaller ones. Numerical results with 65 nm technology show that compared to the conventional SRAM sizing, approximately 2% better accuracy in AlexNet is achieved using heterogeneous SRAM sizing under 500mV of supply voltage.

Original languageEnglish
Title of host publicationProceedings - International SoC Design Conference 2017, ISOCC 2017
PublisherInstitute of Electrical and Electronics Engineers Inc.
Number of pages2
ISBN (Electronic)9781538622858
Publication statusPublished - 2018 May 29
Event14th International SoC Design Conference, ISOCC 2017 - Seoul, Korea, Republic of
Duration: 2017 Nov 52017 Nov 8


Other14th International SoC Design Conference, ISOCC 2017
CountryKorea, Republic of


  • Convolutional neural network
  • Deep neural network
  • Heterogeneous SRAM

ASJC Scopus subject areas

  • Hardware and Architecture
  • Electrical and Electronic Engineering
  • Electronic, Optical and Magnetic Materials

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