TY - GEN
T1 - An efficient convolutional neural networks design with heterogeneous SRAM cell sizing
AU - Choi, Wonseok
AU - Park, Jongsun
N1 - Publisher Copyright:
© 2017 IEEE.
PY - 2018/5/29
Y1 - 2018/5/29
N2 - Deep neural networks (DNNs) have been recently achieving state-of-the-art performance for many artificial intelligence (AI) applications such as computer vision, image recognition, and machine translator. Among them, image recognition using convolutional neural networks (CNNs) is widely used, but the implementation of CNN accelerator for mobile devices is largely restricted due to its intensive computation complexity and a large amount of memory access. In this paper, we adopt the heterogeneous SRAM sizing approach for the memories in CNN processor, where more important higher order data bits are stored in the relatively larger SRAM bit-cells and the less important bits are stored in the smaller ones. Numerical results with 65 nm technology show that compared to the conventional SRAM sizing, approximately 2% better accuracy in AlexNet is achieved using heterogeneous SRAM sizing under 500mV of supply voltage.
AB - Deep neural networks (DNNs) have been recently achieving state-of-the-art performance for many artificial intelligence (AI) applications such as computer vision, image recognition, and machine translator. Among them, image recognition using convolutional neural networks (CNNs) is widely used, but the implementation of CNN accelerator for mobile devices is largely restricted due to its intensive computation complexity and a large amount of memory access. In this paper, we adopt the heterogeneous SRAM sizing approach for the memories in CNN processor, where more important higher order data bits are stored in the relatively larger SRAM bit-cells and the less important bits are stored in the smaller ones. Numerical results with 65 nm technology show that compared to the conventional SRAM sizing, approximately 2% better accuracy in AlexNet is achieved using heterogeneous SRAM sizing under 500mV of supply voltage.
KW - Convolutional neural network
KW - Deep neural network
KW - Heterogeneous SRAM
UR - http://www.scopus.com/inward/record.url?scp=85048852027&partnerID=8YFLogxK
U2 - 10.1109/ISOCC.2017.8368790
DO - 10.1109/ISOCC.2017.8368790
M3 - Conference contribution
AN - SCOPUS:85048852027
T3 - Proceedings - International SoC Design Conference 2017, ISOCC 2017
SP - 103
EP - 104
BT - Proceedings - International SoC Design Conference 2017, ISOCC 2017
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 14th International SoC Design Conference, ISOCC 2017
Y2 - 5 November 2017 through 8 November 2017
ER -