An efficient convolutional neural networks design with heterogeneous SRAM cell sizing

Wonseok Choi; Jongsun Park

doi:10.1109/ISOCC.2017.8368790

An efficient convolutional neural networks design with heterogeneous SRAM cell sizing

Wonseok Choi, Jongsun Park

School of Electrical Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

5 Citations (Scopus)

Abstract

Deep neural networks (DNNs) have been recently achieving state-of-the-art performance for many artificial intelligence (AI) applications such as computer vision, image recognition, and machine translator. Among them, image recognition using convolutional neural networks (CNNs) is widely used, but the implementation of CNN accelerator for mobile devices is largely restricted due to its intensive computation complexity and a large amount of memory access. In this paper, we adopt the heterogeneous SRAM sizing approach for the memories in CNN processor, where more important higher order data bits are stored in the relatively larger SRAM bit-cells and the less important bits are stored in the smaller ones. Numerical results with 65 nm technology show that compared to the conventional SRAM sizing, approximately 2% better accuracy in AlexNet is achieved using heterogeneous SRAM sizing under 500mV of supply voltage.

Original language	English
Title of host publication	Proceedings - International SoC Design Conference 2017, ISOCC 2017
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	103-104
Number of pages	2
ISBN (Electronic)	9781538622858
DOIs	https://doi.org/10.1109/ISOCC.2017.8368790
Publication status	Published - 2018 May 29
Event	14th International SoC Design Conference, ISOCC 2017 - Seoul, Korea, Republic of Duration: 2017 Nov 5 → 2017 Nov 8

Publication series

Name	Proceedings - International SoC Design Conference 2017, ISOCC 2017

Other

Other	14th International SoC Design Conference, ISOCC 2017
Country/Territory	Korea, Republic of
City	Seoul
Period	17/11/5 → 17/11/8

Keywords

Convolutional neural network
Deep neural network
Heterogeneous SRAM

ASJC Scopus subject areas

Hardware and Architecture
Electrical and Electronic Engineering
Electronic, Optical and Magnetic Materials

Access to Document

10.1109/ISOCC.2017.8368790

Cite this

An efficient convolutional neural networks design with heterogeneous SRAM cell sizing. / Choi, Wonseok; Park, Jongsun.

Proceedings - International SoC Design Conference 2017, ISOCC 2017. Institute of Electrical and Electronics Engineers Inc., 2018. p. 103-104 (Proceedings - International SoC Design Conference 2017, ISOCC 2017).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Choi, W & Park, J 2018, An efficient convolutional neural networks design with heterogeneous SRAM cell sizing. in Proceedings - International SoC Design Conference 2017, ISOCC 2017. Proceedings - International SoC Design Conference 2017, ISOCC 2017, Institute of Electrical and Electronics Engineers Inc., pp. 103-104, 14th International SoC Design Conference, ISOCC 2017, Seoul, Korea, Republic of, 17/11/5. https://doi.org/10.1109/ISOCC.2017.8368790

@inproceedings{41a8fd3436cc4a67ae58947913ae3b11,

title = "An efficient convolutional neural networks design with heterogeneous SRAM cell sizing",

abstract = "Deep neural networks (DNNs) have been recently achieving state-of-the-art performance for many artificial intelligence (AI) applications such as computer vision, image recognition, and machine translator. Among them, image recognition using convolutional neural networks (CNNs) is widely used, but the implementation of CNN accelerator for mobile devices is largely restricted due to its intensive computation complexity and a large amount of memory access. In this paper, we adopt the heterogeneous SRAM sizing approach for the memories in CNN processor, where more important higher order data bits are stored in the relatively larger SRAM bit-cells and the less important bits are stored in the smaller ones. Numerical results with 65 nm technology show that compared to the conventional SRAM sizing, approximately 2% better accuracy in AlexNet is achieved using heterogeneous SRAM sizing under 500mV of supply voltage.",

keywords = "Convolutional neural network, Deep neural network, Heterogeneous SRAM",

author = "Wonseok Choi and Jongsun Park",

note = "Publisher Copyright: {\textcopyright} 2017 IEEE.; 14th International SoC Design Conference, ISOCC 2017 ; Conference date: 05-11-2017 Through 08-11-2017",

year = "2018",

month = may,

day = "29",

doi = "10.1109/ISOCC.2017.8368790",

language = "English",

series = "Proceedings - International SoC Design Conference 2017, ISOCC 2017",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

pages = "103--104",

booktitle = "Proceedings - International SoC Design Conference 2017, ISOCC 2017",

}

TY - GEN

T1 - An efficient convolutional neural networks design with heterogeneous SRAM cell sizing

AU - Choi, Wonseok

AU - Park, Jongsun

PY - 2018/5/29

Y1 - 2018/5/29

N2 - Deep neural networks (DNNs) have been recently achieving state-of-the-art performance for many artificial intelligence (AI) applications such as computer vision, image recognition, and machine translator. Among them, image recognition using convolutional neural networks (CNNs) is widely used, but the implementation of CNN accelerator for mobile devices is largely restricted due to its intensive computation complexity and a large amount of memory access. In this paper, we adopt the heterogeneous SRAM sizing approach for the memories in CNN processor, where more important higher order data bits are stored in the relatively larger SRAM bit-cells and the less important bits are stored in the smaller ones. Numerical results with 65 nm technology show that compared to the conventional SRAM sizing, approximately 2% better accuracy in AlexNet is achieved using heterogeneous SRAM sizing under 500mV of supply voltage.

AB - Deep neural networks (DNNs) have been recently achieving state-of-the-art performance for many artificial intelligence (AI) applications such as computer vision, image recognition, and machine translator. Among them, image recognition using convolutional neural networks (CNNs) is widely used, but the implementation of CNN accelerator for mobile devices is largely restricted due to its intensive computation complexity and a large amount of memory access. In this paper, we adopt the heterogeneous SRAM sizing approach for the memories in CNN processor, where more important higher order data bits are stored in the relatively larger SRAM bit-cells and the less important bits are stored in the smaller ones. Numerical results with 65 nm technology show that compared to the conventional SRAM sizing, approximately 2% better accuracy in AlexNet is achieved using heterogeneous SRAM sizing under 500mV of supply voltage.

KW - Convolutional neural network

KW - Deep neural network

KW - Heterogeneous SRAM

UR - http://www.scopus.com/inward/record.url?scp=85048852027&partnerID=8YFLogxK

U2 - 10.1109/ISOCC.2017.8368790

DO - 10.1109/ISOCC.2017.8368790

M3 - Conference contribution

AN - SCOPUS:85048852027

T3 - Proceedings - International SoC Design Conference 2017, ISOCC 2017

SP - 103

EP - 104

BT - Proceedings - International SoC Design Conference 2017, ISOCC 2017

PB - Institute of Electrical and Electronics Engineers Inc.

T2 - 14th International SoC Design Conference, ISOCC 2017

Y2 - 5 November 2017 through 8 November 2017

ER -

An efficient convolutional neural networks design with heterogeneous SRAM cell sizing

Abstract

Publication series

Other

Keywords

ASJC Scopus subject areas

Access to Document

Other files and links

Fingerprint

Cite this