This paper presents an efficient memory-address remapping technique for a high-throughput quasi-cyclic low-density parity check (QC-LDPC) decoder. In general, an LDPC decoder needs a large size of embedded memories for the temporal storage of the check node process (CNP) and variable node process (VNP) outputs. To increase the decoder throughput, overlapping the CNP and VNP operations is necessary; however, the parallel operations are mainly restricted by the embedded memory bandwidth. This work presents an efficient memory management approach in an LDPC decoder, where the memory-address conflicts and redundant memory-read operations are effectively reduced by using a proposed memory-address remapping technique. As a result, parallel variable node unit operations significantly increase, leading to higher throughput. When the proposed approach is applied to the various code rates of IEEE std. 802.16-2009, increases in decoding speed of up to 1.52X per iteration are achieved for overlapped message passing algorithm-based architecture, along with considerable reductions in the number of memory-read accesses. Using a 0.13-(Formula presented.)m CMOS process, a QC-LDPC decoder with multi-code rates is implemented, and the experimental results show that the proposed decoder achieves considerable throughput area ratio increase with energy savings compared to the conventional approaches.
- LDPC decoder
- Low-density parity check (LDPC) codes
- Overlapped message passing (OMP)
- Quasi-cyclic (QC) codes
ASJC Scopus subject areas
- Signal Processing
- Applied Mathematics