Two main bottlenecks encountered when implementing energy-efficient spike-timing-dependent plasticity (STDP) based sparse coding, are the complex computation of winner-take-all (WTA) operation and repetitive neuronal operations in the time domain processing. In this paper, we present an energy-efficient STDP based sparse coding processor. The low-cost hardware is based on algorithmic reduction techniques as following: First, the complex WTA operation is simplified based on the prediction of spike emitting neurons. Sparsity based approximation in spatial and temporal domain are also efficiently exploited to remove the redundant neurons with negligible algorithmic accuracy loss. We designed and implemented the hardware of the STDP based sparse coding using 65nm CMOS process. By exploiting input sparsity, the proposed architecture can dynamically trade off computation energy (up to 74%) with algorithmic quality for Natural image (maximum 3.55% quality loss) and MNIST (no quality loss) applications. In the inference mode of operations, the SNN hardware achieves the throughput of 374Mpixels/s and 840.2GSOP/s with energy-efficiency of 781.52pJ/pixel and 0.35pJ/SOP.