An Energy-efficient On-chip Learning Architecture for STDP based Sparse Coding

Heetak Kim, Hoyoung Tang, Jongsun Park

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

Two main bottlenecks encountered when implementing energy-efficient spike-timing-dependent plasticity (STDP) based sparse coding, are the complex computation of winner-take-all (WTA) operation and repetitive neuronal operations in the time domain processing. In this paper, we present an energy-efficient STDP based sparse coding processor. The low-cost hardware is based on algorithmic reduction techniques as following: First, the complex WTA operation is simplified based on the prediction of spike emitting neurons. Sparsity based approximation in spatial and temporal domain are also efficiently exploited to remove the redundant neurons with negligible algorithmic accuracy loss. We designed and implemented the hardware of the STDP based sparse coding using 65nm CMOS process. By exploiting input sparsity, the proposed architecture can dynamically trade off computation energy (up to 74%) with algorithmic quality for Natural image (maximum 3.55% quality loss) and MNIST (no quality loss) applications. In the inference mode of operations, the SNN hardware achieves the throughput of 374Mpixels/s and 840.2GSOP/s with energy-efficiency of 781.52pJ/pixel and 0.35pJ/SOP.

Original languageEnglish
Title of host publicationInternational Symposium on Low Power Electronics and Design, ISLPED 2019
PublisherInstitute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)9781728129549
DOIs
Publication statusPublished - 2019 Jul
Event2019 IEEE/ACM International Symposium on Low Power Electronics and Design, ISLPED 2019 - Lausanne, Switzerland
Duration: 2019 Jul 292019 Jul 31

Publication series

NameProceedings of the International Symposium on Low Power Electronics and Design
Volume2019-July
ISSN (Print)1533-4678

Conference

Conference2019 IEEE/ACM International Symposium on Low Power Electronics and Design, ISLPED 2019
CountrySwitzerland
CityLausanne
Period19/7/2919/7/31

Keywords

  • On-chip learning
  • Sparse coding
  • Spike timing dependent plasticity
  • Spiking neural network

ASJC Scopus subject areas

  • Engineering(all)

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    Kim, H., Tang, H., & Park, J. (2019). An Energy-efficient On-chip Learning Architecture for STDP based Sparse Coding. In International Symposium on Low Power Electronics and Design, ISLPED 2019 [8824938] (Proceedings of the International Symposium on Low Power Electronics and Design; Vol. 2019-July). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ISLPED.2019.8824938