TY - JOUR
T1 - An Even/Odd Error Detection Based Low-Complexity Chase Decoding for Low-Latency RS Decoder Design
AU - Jeong, Jinho
AU - Shin, Dongyeob
AU - Shin, Wongyu
AU - Park, Jongsun
N1 - Funding Information:
Manuscript received December 24, 2020; accepted January 13, 2021. Date of publication January 26, 2021; date of current version May 6, 2021. This work was supported in part by SK Hynix, in part by the National Research Foundation of Korea grant funded by the Korea government (No. NRF-2020R1A2C3014820), and in part by the MSIT (Ministry of Science and ICT), Korea, under the ITRC (Information Technology Research Center) support program (IITP-2020-2018-0-01433) supervised by the IITP (Institute for Information & communications Technology Promotion). The associate editor coordinating the review of this letter and approving it for publication was K. Niu. (Corresponding author: Jongsun Park.) Jinho Jeong and Jongsun Park are with the School of Electrical Engineering, Korea University, Seoul 02841, South Korea (e-mail: k007312@korea.ac.kr; jongsun@korea.ac.kr).
Publisher Copyright:
© 1997-2012 IEEE.
PY - 2021/5
Y1 - 2021/5
N2 - This letter presents a modified low-complexity chase (LCC) algorithm, where a fewer number of vectors can be tested with minor error correction performance degradation. The proposed LCC decoding pre-determines whether the number of errors in the received codeword is even or odd, and it processes only necessary test vectors. As a result, the number of test vectors can be reduced by half compared to the conventional LCC decoding. The Reed-Solomon (255,239) decoder with the proposed LCC algorithm has been implemented using 65nm CMOS process. The hardware implementation results show that the proposed decoder shows 48.5% reduced latency with 0.06 dB of coding gain decrease at $\mathbf {10^{-6}}$ codeword error rate compared to the state-of-the-art LCC decoder.
AB - This letter presents a modified low-complexity chase (LCC) algorithm, where a fewer number of vectors can be tested with minor error correction performance degradation. The proposed LCC decoding pre-determines whether the number of errors in the received codeword is even or odd, and it processes only necessary test vectors. As a result, the number of test vectors can be reduced by half compared to the conventional LCC decoding. The Reed-Solomon (255,239) decoder with the proposed LCC algorithm has been implemented using 65nm CMOS process. The hardware implementation results show that the proposed decoder shows 48.5% reduced latency with 0.06 dB of coding gain decrease at $\mathbf {10^{-6}}$ codeword error rate compared to the state-of-the-art LCC decoder.
KW - Reed-Solomon (RS) codes
KW - algebraic soft-decision decoding (ASD)
KW - latency
KW - low-complexity chase (LCC)
UR - http://www.scopus.com/inward/record.url?scp=85100450037&partnerID=8YFLogxK
U2 - 10.1109/LCOMM.2021.3054753
DO - 10.1109/LCOMM.2021.3054753
M3 - Article
AN - SCOPUS:85100450037
SN - 1089-7798
VL - 25
SP - 1505
EP - 1509
JO - IEEE Communications Letters
JF - IEEE Communications Letters
IS - 5
M1 - 9336031
ER -