An improved VLSI architecture for Viterbi decoder

Byonghyo Shim, Sungmin Cho, Jung Chul Suh

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Citation (Scopus)

Abstract

An improved VLSI architecture for a high-speed Viterbi decoder is proposed. We partitioned the datapath of the Viterbi decoder into largely 3 pipeline stages and to reduce the operation overhead of the add-compare-select unit (ACSU), removed the minimum metric selection logic and exploited the constant subtraction scheme for the metric rescaling. This can be done by using unsigned arithmetic and the overflow detection unit. We also discussed the uselessness of the minimum metric selection logic in the analysis of truncation effects. Simulation results demonstrated that if the traceback depth is long enough, the arbitrary state decoding can be used without many disadvantages over the best state decoding. The survival memory unit (SMU) pipelining architecture based on the modified traceback algorithm is also presented. By exploiting the two registers and multiplexers, we made a one-stage pipeline cell and by cascading them, a traceback operation without LIFO or a complex memory controller can be achieved with a latency of only 2T.

Original languageEnglish
Title of host publicationIEEE Region 10 Annual International Conference, Proceedings/TENCON
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages259-262
Number of pages4
Volume1
ISBN (Electronic)0780357396, 9780780357396
DOIs
Publication statusPublished - 1999 Jan 1
Externally publishedYes
Event1999 IEEE Region 10 Conference, TENCON 1999 - Cheju Island, Korea, Republic of
Duration: 1999 Sep 151999 Sep 17

Other

Other1999 IEEE Region 10 Conference, TENCON 1999
CountryKorea, Republic of
CityCheju Island
Period99/9/1599/9/17

Fingerprint

Decoding
Pipelines
Data storage equipment
Controllers

ASJC Scopus subject areas

  • Computer Science Applications
  • Electrical and Electronic Engineering

Cite this

Shim, B., Cho, S., & Suh, J. C. (1999). An improved VLSI architecture for Viterbi decoder. In IEEE Region 10 Annual International Conference, Proceedings/TENCON (Vol. 1, pp. 259-262). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/TENCON.1999.818399

An improved VLSI architecture for Viterbi decoder. / Shim, Byonghyo; Cho, Sungmin; Suh, Jung Chul.

IEEE Region 10 Annual International Conference, Proceedings/TENCON. Vol. 1 Institute of Electrical and Electronics Engineers Inc., 1999. p. 259-262.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Shim, B, Cho, S & Suh, JC 1999, An improved VLSI architecture for Viterbi decoder. in IEEE Region 10 Annual International Conference, Proceedings/TENCON. vol. 1, Institute of Electrical and Electronics Engineers Inc., pp. 259-262, 1999 IEEE Region 10 Conference, TENCON 1999, Cheju Island, Korea, Republic of, 99/9/15. https://doi.org/10.1109/TENCON.1999.818399
Shim B, Cho S, Suh JC. An improved VLSI architecture for Viterbi decoder. In IEEE Region 10 Annual International Conference, Proceedings/TENCON. Vol. 1. Institute of Electrical and Electronics Engineers Inc. 1999. p. 259-262 https://doi.org/10.1109/TENCON.1999.818399
Shim, Byonghyo ; Cho, Sungmin ; Suh, Jung Chul. / An improved VLSI architecture for Viterbi decoder. IEEE Region 10 Annual International Conference, Proceedings/TENCON. Vol. 1 Institute of Electrical and Electronics Engineers Inc., 1999. pp. 259-262
@inproceedings{a622334cfda34aee9d09ffc9f1fccd73,
title = "An improved VLSI architecture for Viterbi decoder",
abstract = "An improved VLSI architecture for a high-speed Viterbi decoder is proposed. We partitioned the datapath of the Viterbi decoder into largely 3 pipeline stages and to reduce the operation overhead of the add-compare-select unit (ACSU), removed the minimum metric selection logic and exploited the constant subtraction scheme for the metric rescaling. This can be done by using unsigned arithmetic and the overflow detection unit. We also discussed the uselessness of the minimum metric selection logic in the analysis of truncation effects. Simulation results demonstrated that if the traceback depth is long enough, the arbitrary state decoding can be used without many disadvantages over the best state decoding. The survival memory unit (SMU) pipelining architecture based on the modified traceback algorithm is also presented. By exploiting the two registers and multiplexers, we made a one-stage pipeline cell and by cascading them, a traceback operation without LIFO or a complex memory controller can be achieved with a latency of only 2T.",
author = "Byonghyo Shim and Sungmin Cho and Suh, {Jung Chul}",
year = "1999",
month = "1",
day = "1",
doi = "10.1109/TENCON.1999.818399",
language = "English",
volume = "1",
pages = "259--262",
booktitle = "IEEE Region 10 Annual International Conference, Proceedings/TENCON",
publisher = "Institute of Electrical and Electronics Engineers Inc.",

}

TY - GEN

T1 - An improved VLSI architecture for Viterbi decoder

AU - Shim, Byonghyo

AU - Cho, Sungmin

AU - Suh, Jung Chul

PY - 1999/1/1

Y1 - 1999/1/1

N2 - An improved VLSI architecture for a high-speed Viterbi decoder is proposed. We partitioned the datapath of the Viterbi decoder into largely 3 pipeline stages and to reduce the operation overhead of the add-compare-select unit (ACSU), removed the minimum metric selection logic and exploited the constant subtraction scheme for the metric rescaling. This can be done by using unsigned arithmetic and the overflow detection unit. We also discussed the uselessness of the minimum metric selection logic in the analysis of truncation effects. Simulation results demonstrated that if the traceback depth is long enough, the arbitrary state decoding can be used without many disadvantages over the best state decoding. The survival memory unit (SMU) pipelining architecture based on the modified traceback algorithm is also presented. By exploiting the two registers and multiplexers, we made a one-stage pipeline cell and by cascading them, a traceback operation without LIFO or a complex memory controller can be achieved with a latency of only 2T.

AB - An improved VLSI architecture for a high-speed Viterbi decoder is proposed. We partitioned the datapath of the Viterbi decoder into largely 3 pipeline stages and to reduce the operation overhead of the add-compare-select unit (ACSU), removed the minimum metric selection logic and exploited the constant subtraction scheme for the metric rescaling. This can be done by using unsigned arithmetic and the overflow detection unit. We also discussed the uselessness of the minimum metric selection logic in the analysis of truncation effects. Simulation results demonstrated that if the traceback depth is long enough, the arbitrary state decoding can be used without many disadvantages over the best state decoding. The survival memory unit (SMU) pipelining architecture based on the modified traceback algorithm is also presented. By exploiting the two registers and multiplexers, we made a one-stage pipeline cell and by cascading them, a traceback operation without LIFO or a complex memory controller can be achieved with a latency of only 2T.

UR - http://www.scopus.com/inward/record.url?scp=33646229437&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=33646229437&partnerID=8YFLogxK

U2 - 10.1109/TENCON.1999.818399

DO - 10.1109/TENCON.1999.818399

M3 - Conference contribution

VL - 1

SP - 259

EP - 262

BT - IEEE Region 10 Annual International Conference, Proceedings/TENCON

PB - Institute of Electrical and Electronics Engineers Inc.

ER -