An innovative instruction cache for embedded processors

Cheol Hong Kim, Sung Woo Jung, Chu Shik Jhon

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

In this paper we present a methodology to enable the design of power efficient instruction cache for embedded processors. The proposed technique, which splits the instruction cache into several small sub-caches, utilizes the locality of applications to reduce dynamic energy consumption in the instruction cache. The proposed cache reduces dynamic energy consumption by accessing only one sub-cache when a request comes into the cache. It also reduces dynamic energy consumption by eliminating the energy consumed in tag matching. In addition, we propose the technique to reduce leakage energy consumption in the proposed cache. We evaluate the design using a simulation infrastructure based on SimpleScalar and CACTI. Simulation results show that the proposed cache reduces dynamic energy by 42% - 59% and reduces leakage energy by 70% - 80%.

Original languageEnglish
Title of host publicationLecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)
Pages41-51
Number of pages11
Volume3740 LNCS
Publication statusPublished - 2005 Dec 1
Externally publishedYes
Event10th Asia-Pacific Conference on Advances in Computer Systems Architecture, ACSAC 2005 - Singapore, Singapore
Duration: 2005 Oct 242005 Oct 26

Publication series

NameLecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)
Volume3740 LNCS
ISSN (Print)03029743
ISSN (Electronic)16113349

Other

Other10th Asia-Pacific Conference on Advances in Computer Systems Architecture, ACSAC 2005
CountrySingapore
CitySingapore
Period05/10/2405/10/26

Fingerprint

Embedded Processor
Cache
Energy utilization
Energy Consumption
Leakage
Energy
Locality
Simulation
Infrastructure
Methodology
Evaluate

ASJC Scopus subject areas

  • Biochemistry, Genetics and Molecular Biology(all)
  • Computer Science(all)
  • Theoretical Computer Science

Cite this

Kim, C. H., Jung, S. W., & Jhon, C. S. (2005). An innovative instruction cache for embedded processors. In Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics) (Vol. 3740 LNCS, pp. 41-51). (Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics); Vol. 3740 LNCS).

An innovative instruction cache for embedded processors. / Kim, Cheol Hong; Jung, Sung Woo; Jhon, Chu Shik.

Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics). Vol. 3740 LNCS 2005. p. 41-51 (Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics); Vol. 3740 LNCS).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Kim, CH, Jung, SW & Jhon, CS 2005, An innovative instruction cache for embedded processors. in Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics). vol. 3740 LNCS, Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics), vol. 3740 LNCS, pp. 41-51, 10th Asia-Pacific Conference on Advances in Computer Systems Architecture, ACSAC 2005, Singapore, Singapore, 05/10/24.
Kim CH, Jung SW, Jhon CS. An innovative instruction cache for embedded processors. In Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics). Vol. 3740 LNCS. 2005. p. 41-51. (Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)).
Kim, Cheol Hong ; Jung, Sung Woo ; Jhon, Chu Shik. / An innovative instruction cache for embedded processors. Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics). Vol. 3740 LNCS 2005. pp. 41-51 (Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)).
@inproceedings{51d3d7db0b7b4de982092607abedd8f7,
title = "An innovative instruction cache for embedded processors",
abstract = "In this paper we present a methodology to enable the design of power efficient instruction cache for embedded processors. The proposed technique, which splits the instruction cache into several small sub-caches, utilizes the locality of applications to reduce dynamic energy consumption in the instruction cache. The proposed cache reduces dynamic energy consumption by accessing only one sub-cache when a request comes into the cache. It also reduces dynamic energy consumption by eliminating the energy consumed in tag matching. In addition, we propose the technique to reduce leakage energy consumption in the proposed cache. We evaluate the design using a simulation infrastructure based on SimpleScalar and CACTI. Simulation results show that the proposed cache reduces dynamic energy by 42{\%} - 59{\%} and reduces leakage energy by 70{\%} - 80{\%}.",
author = "Kim, {Cheol Hong} and Jung, {Sung Woo} and Jhon, {Chu Shik}",
year = "2005",
month = "12",
day = "1",
language = "English",
isbn = "3540296433",
volume = "3740 LNCS",
series = "Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)",
pages = "41--51",
booktitle = "Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)",

}

TY - GEN

T1 - An innovative instruction cache for embedded processors

AU - Kim, Cheol Hong

AU - Jung, Sung Woo

AU - Jhon, Chu Shik

PY - 2005/12/1

Y1 - 2005/12/1

N2 - In this paper we present a methodology to enable the design of power efficient instruction cache for embedded processors. The proposed technique, which splits the instruction cache into several small sub-caches, utilizes the locality of applications to reduce dynamic energy consumption in the instruction cache. The proposed cache reduces dynamic energy consumption by accessing only one sub-cache when a request comes into the cache. It also reduces dynamic energy consumption by eliminating the energy consumed in tag matching. In addition, we propose the technique to reduce leakage energy consumption in the proposed cache. We evaluate the design using a simulation infrastructure based on SimpleScalar and CACTI. Simulation results show that the proposed cache reduces dynamic energy by 42% - 59% and reduces leakage energy by 70% - 80%.

AB - In this paper we present a methodology to enable the design of power efficient instruction cache for embedded processors. The proposed technique, which splits the instruction cache into several small sub-caches, utilizes the locality of applications to reduce dynamic energy consumption in the instruction cache. The proposed cache reduces dynamic energy consumption by accessing only one sub-cache when a request comes into the cache. It also reduces dynamic energy consumption by eliminating the energy consumed in tag matching. In addition, we propose the technique to reduce leakage energy consumption in the proposed cache. We evaluate the design using a simulation infrastructure based on SimpleScalar and CACTI. Simulation results show that the proposed cache reduces dynamic energy by 42% - 59% and reduces leakage energy by 70% - 80%.

UR - http://www.scopus.com/inward/record.url?scp=33646535809&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=33646535809&partnerID=8YFLogxK

M3 - Conference contribution

SN - 3540296433

SN - 9783540296430

VL - 3740 LNCS

T3 - Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)

SP - 41

EP - 51

BT - Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)

ER -