An innovative instruction cache for embedded processors

Cheol Hong Kim, Sung Woo Chung, Chu Shik Jhon

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

In this paper we present a methodology to enable the design of power efficient instruction cache for embedded processors. The proposed technique, which splits the instruction cache into several small sub-caches, utilizes the locality of applications to reduce dynamic energy consumption in the instruction cache. The proposed cache reduces dynamic energy consumption by accessing only one sub-cache when a request comes into the cache. It also reduces dynamic energy consumption by eliminating the energy consumed in tag matching. In addition, we propose the technique to reduce leakage energy consumption in the proposed cache. We evaluate the design using a simulation infrastructure based on SimpleScalar and CACTI. Simulation results show that the proposed cache reduces dynamic energy by 42% - 59% and reduces leakage energy by 70% - 80%.

Original languageEnglish
Title of host publicationAdvances in Computer Systems Architecture - 10th Asia-Pacific Conference, ACSAC 2005, Proceedings
Pages41-51
Number of pages11
Publication statusPublished - 2005
Externally publishedYes
Event10th Asia-Pacific Conference on Advances in Computer Systems Architecture, ACSAC 2005 - Singapore, Singapore
Duration: 2005 Oct 242005 Oct 26

Publication series

NameLecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)
Volume3740 LNCS
ISSN (Print)0302-9743
ISSN (Electronic)1611-3349

Other

Other10th Asia-Pacific Conference on Advances in Computer Systems Architecture, ACSAC 2005
CountrySingapore
CitySingapore
Period05/10/2405/10/26

ASJC Scopus subject areas

  • Theoretical Computer Science
  • Computer Science(all)

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