TY - GEN
T1 - An innovative instruction cache for embedded processors
AU - Kim, Cheol Hong
AU - Chung, Sung Woo
AU - Jhon, Chu Shik
PY - 2005
Y1 - 2005
N2 - In this paper we present a methodology to enable the design of power efficient instruction cache for embedded processors. The proposed technique, which splits the instruction cache into several small sub-caches, utilizes the locality of applications to reduce dynamic energy consumption in the instruction cache. The proposed cache reduces dynamic energy consumption by accessing only one sub-cache when a request comes into the cache. It also reduces dynamic energy consumption by eliminating the energy consumed in tag matching. In addition, we propose the technique to reduce leakage energy consumption in the proposed cache. We evaluate the design using a simulation infrastructure based on SimpleScalar and CACTI. Simulation results show that the proposed cache reduces dynamic energy by 42% - 59% and reduces leakage energy by 70% - 80%.
AB - In this paper we present a methodology to enable the design of power efficient instruction cache for embedded processors. The proposed technique, which splits the instruction cache into several small sub-caches, utilizes the locality of applications to reduce dynamic energy consumption in the instruction cache. The proposed cache reduces dynamic energy consumption by accessing only one sub-cache when a request comes into the cache. It also reduces dynamic energy consumption by eliminating the energy consumed in tag matching. In addition, we propose the technique to reduce leakage energy consumption in the proposed cache. We evaluate the design using a simulation infrastructure based on SimpleScalar and CACTI. Simulation results show that the proposed cache reduces dynamic energy by 42% - 59% and reduces leakage energy by 70% - 80%.
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M3 - Conference contribution
AN - SCOPUS:33646535809
SN - 3540296433
SN - 9783540296430
T3 - Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)
SP - 41
EP - 51
BT - Advances in Computer Systems Architecture - 10th Asia-Pacific Conference, ACSAC 2005, Proceedings
T2 - 10th Asia-Pacific Conference on Advances in Computer Systems Architecture, ACSAC 2005
Y2 - 24 October 2005 through 26 October 2005
ER -