Abstract
In this paper we present a methodology to enable the design of power efficient instruction cache for embedded processors. The proposed technique, which splits the instruction cache into several small sub-caches, utilizes the locality of applications to reduce dynamic energy consumption in the instruction cache. The proposed cache reduces dynamic energy consumption by accessing only one sub-cache when a request comes into the cache. It also reduces dynamic energy consumption by eliminating the energy consumed in tag matching. In addition, we propose the technique to reduce leakage energy consumption in the proposed cache. We evaluate the design using a simulation infrastructure based on SimpleScalar and CACTI. Simulation results show that the proposed cache reduces dynamic energy by 42% - 59% and reduces leakage energy by 70% - 80%.
| Original language | English |
|---|---|
| Title of host publication | Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics) |
| Pages | 41-51 |
| Number of pages | 11 |
| Volume | 3740 LNCS |
| Publication status | Published - 2005 Dec 1 |
| Externally published | Yes |
| Event | 10th Asia-Pacific Conference on Advances in Computer Systems Architecture, ACSAC 2005 - Singapore, Singapore Duration: 2005 Oct 24 → 2005 Oct 26 |
Publication series
| Name | Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics) |
|---|---|
| Volume | 3740 LNCS |
| ISSN (Print) | 03029743 |
| ISSN (Electronic) | 16113349 |
Other
| Other | 10th Asia-Pacific Conference on Advances in Computer Systems Architecture, ACSAC 2005 |
|---|---|
| Country | Singapore |
| City | Singapore |
| Period | 05/10/24 → 05/10/26 |
Fingerprint
ASJC Scopus subject areas
- Biochemistry, Genetics and Molecular Biology(all)
- Computer Science(all)
- Theoretical Computer Science
Cite this
An innovative instruction cache for embedded processors. / Kim, Cheol Hong; Jung, Sung Woo; Jhon, Chu Shik.
Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics). Vol. 3740 LNCS 2005. p. 41-51 (Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics); Vol. 3740 LNCS).Research output: Chapter in Book/Report/Conference proceeding › Conference contribution
}
TY - GEN
T1 - An innovative instruction cache for embedded processors
AU - Kim, Cheol Hong
AU - Jung, Sung Woo
AU - Jhon, Chu Shik
PY - 2005/12/1
Y1 - 2005/12/1
N2 - In this paper we present a methodology to enable the design of power efficient instruction cache for embedded processors. The proposed technique, which splits the instruction cache into several small sub-caches, utilizes the locality of applications to reduce dynamic energy consumption in the instruction cache. The proposed cache reduces dynamic energy consumption by accessing only one sub-cache when a request comes into the cache. It also reduces dynamic energy consumption by eliminating the energy consumed in tag matching. In addition, we propose the technique to reduce leakage energy consumption in the proposed cache. We evaluate the design using a simulation infrastructure based on SimpleScalar and CACTI. Simulation results show that the proposed cache reduces dynamic energy by 42% - 59% and reduces leakage energy by 70% - 80%.
AB - In this paper we present a methodology to enable the design of power efficient instruction cache for embedded processors. The proposed technique, which splits the instruction cache into several small sub-caches, utilizes the locality of applications to reduce dynamic energy consumption in the instruction cache. The proposed cache reduces dynamic energy consumption by accessing only one sub-cache when a request comes into the cache. It also reduces dynamic energy consumption by eliminating the energy consumed in tag matching. In addition, we propose the technique to reduce leakage energy consumption in the proposed cache. We evaluate the design using a simulation infrastructure based on SimpleScalar and CACTI. Simulation results show that the proposed cache reduces dynamic energy by 42% - 59% and reduces leakage energy by 70% - 80%.
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UR - http://www.scopus.com/inward/citedby.url?scp=33646535809&partnerID=8YFLogxK
M3 - Conference contribution
SN - 3540296433
SN - 9783540296430
VL - 3740 LNCS
T3 - Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)
SP - 41
EP - 51
BT - Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)
ER -