Abstract
In this paper we present a methodology to enable the design of power efficient instruction cache for embedded processors. The proposed technique, which splits the instruction cache into several small sub-caches, utilizes the locality of applications to reduce dynamic energy consumption in the instruction cache. The proposed cache reduces dynamic energy consumption by accessing only one sub-cache when a request comes into the cache. It also reduces dynamic energy consumption by eliminating the energy consumed in tag matching. In addition, we propose the technique to reduce leakage energy consumption in the proposed cache. We evaluate the design using a simulation infrastructure based on SimpleScalar and CACTI. Simulation results show that the proposed cache reduces dynamic energy by 42% - 59% and reduces leakage energy by 70% - 80%.
| Original language | English |
|---|---|
| Title of host publication | Advances in Computer Systems Architecture - 10th Asia-Pacific Conference, ACSAC 2005, Proceedings |
| Pages | 41-51 |
| Number of pages | 11 |
| Publication status | Published - 2005 |
| Externally published | Yes |
| Event | 10th Asia-Pacific Conference on Advances in Computer Systems Architecture, ACSAC 2005 - Singapore, Singapore Duration: 2005 Oct 24 → 2005 Oct 26 |
Publication series
| Name | Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics) |
|---|---|
| Volume | 3740 LNCS |
| ISSN (Print) | 0302-9743 |
| ISSN (Electronic) | 1611-3349 |
Other
| Other | 10th Asia-Pacific Conference on Advances in Computer Systems Architecture, ACSAC 2005 |
|---|---|
| Country | Singapore |
| City | Singapore |
| Period | 05/10/24 → 05/10/26 |
ASJC Scopus subject areas
- Theoretical Computer Science
- Computer Science(all)
UN SDGs
This output contributes to the following Sustainable Development Goal(s)
