An inverter layout technique for propagation delay minimization

Ji Hak Yu, Chan Keun Kwon, Junil Moon, Soo-Won Kim

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

Through various cases of inverter layout, the change in the propagation delay time (tPD) in the ring oscillator that consists of inverters can be analyzed. In this paper, an inverter layout technique for tPD minimization is presented. Through the case-by-case layout, to reduce the tPD, we propose that layout engineers should reduce the input and output node length. The proposed technique post-simulated in a 0.18um CMOS process achieves maximum 7.318% reduced tPD compared to the basic inverter layout.

Original languageEnglish
Title of host publication2015 International Symposium on Consumer Electronics, ISCE 2015
PublisherInstitute of Electrical and Electronics Engineers Inc.
Volume2015-August
ISBN (Electronic)9781467373654
DOIs
Publication statusPublished - 2015 Aug 4
EventIEEE International Symposium on Consumer Electronics, ISCE 2015 - Madrid, Spain
Duration: 2015 Jun 242015 Jun 26

Other

OtherIEEE International Symposium on Consumer Electronics, ISCE 2015
CountrySpain
CityMadrid
Period15/6/2415/6/26

Keywords

  • inverter
  • layout
  • Propagation delay
  • Ring oscillator

ASJC Scopus subject areas

  • Engineering(all)

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    Yu, J. H., Kwon, C. K., Moon, J., & Kim, S-W. (2015). An inverter layout technique for propagation delay minimization. In 2015 International Symposium on Consumer Electronics, ISCE 2015 (Vol. 2015-August). [7177790] Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ISCE.2015.7177790