Analog CMOS-based resistive processing unit for deep neural network training

Seyoung Kim, Tayfun Gokmen, Hyung Min Lee, Wilfried E. Haensch

Research output: Chapter in Book/Report/Conference proceedingConference contribution

17 Citations (Scopus)

Abstract

Recently we have shown that an architecture based on resistive processing unit (RPU) devices has potential to achieve significant acceleration in deep neural network (DNN) training compared to today's software-based DNN implementations running on CPU/GPU. However, currently available device candidates based on non-volatile memory technologies do not satisfy all the requirements to realize the RPU concept. Here, we propose an analog CMOS-based RPU design (CMOS RPU) which can store and process data locally and can be operated in a massively parallel manner. We analyze various properties of the CMOS RPU to evaluate the functionality and feasibility for acceleration of DNN training.

Original languageEnglish
Title of host publication2017 IEEE 60th International Midwest Symposium on Circuits and Systems, MWSCAS 2017
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages422-425
Number of pages4
ISBN (Electronic)9781509063895
DOIs
Publication statusPublished - 2017 Sep 27
Event60th IEEE International Midwest Symposium on Circuits and Systems, MWSCAS 2017 - Boston, United States
Duration: 2017 Aug 62017 Aug 9

Publication series

NameMidwest Symposium on Circuits and Systems
Volume2017-August
ISSN (Print)1548-3746

Conference

Conference60th IEEE International Midwest Symposium on Circuits and Systems, MWSCAS 2017
CountryUnited States
CityBoston
Period17/8/617/8/9

Keywords

  • Deep neural network
  • Machine learning accelerator
  • Resistive memory
  • Resistive processing unit
  • RPU

ASJC Scopus subject areas

  • Electronic, Optical and Magnetic Materials
  • Electrical and Electronic Engineering

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